公开(公告)号：US20180337166A1

公开(公告)日：2018-11-22

申请号：US16048037

申请日：2018-07-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michel Koopmans

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L21/66 ,  H01L21/78 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/14 ,  H01L24/80 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68354 ,  H01L2221/68395 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/95001

Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.

公开(公告)号：US10126357B2

公开(公告)日：2018-11-13

申请号：US15660387

申请日：2017-07-26

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans ,  James M. Derderian

IPC: G01R31/28 ,  G01R1/073

Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

公开(公告)号：US09818625B2

公开(公告)日：2017-11-14

申请号：US15059076

申请日：2016-03-02

Applicant: Micron Technology, Inc.

Inventor： Jian Li ,  Steven K. Groothuis ,  Michel Koopmans

IPC: H01L21/48 ,  H01L23/42 ,  H01L21/56 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/433 ,  H01L23/538 ,  H01L23/31 ,  H01L23/427 ,  H01L23/498

CPC classification number: H01L21/4882 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16257 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

公开(公告)号：US09659917B1

公开(公告)日：2017-05-23

申请号：US14967009

申请日：2015-12-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michel Koopmans

IPC: H01L21/78 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/14 ,  H01L24/80 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68354 ,  H01L2221/68395 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/95001

Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.

公开(公告)号：US20160141270A1

公开(公告)日：2016-05-19

申请号：US15007615

申请日：2016-01-27

Applicant: Micron Technology, Inc.

Inventor： Michel Koopmans ,  Shijian Luo ,  David R. Hembree

IPC: H01L25/065 ,  H01L23/373 ,  H01L25/00 ,  H01L23/522

CPC classification number: H01L25/0652 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/01047

Abstract: Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.

公开(公告)号：US09287240B2

公开(公告)日：2016-03-15

申请号：US14105940

申请日：2013-12-13

Applicant: Micron Technology, Inc.

Inventor： Jian Li ,  Steven K. Groothuis ,  Michel Koopmans

IPC: H01L23/373 ,  H01L25/065 ,  H01L23/36 ,  H01L23/42 ,  H01L23/433 ,  H01L23/538 ,  H01L23/31 ,  H01L23/427 ,  H01L23/498

CPC classification number: H01L21/4882 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16257 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

Abstract translation: 本文公开了具有热隔离件和相关联的系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括限定空腔的导热壳体，腔内的第一半导体管芯的堆叠，以及相对于第一管芯堆叠堆叠并由封装衬底承载的第二半导体管芯。 半导体管芯组件还包括设置在封装衬底和导热壳体之间的热隔离件。 热隔离物可以包括半导体衬底和延伸穿过半导体衬底并且电耦合到第一半导体管芯，第二半导体管芯和封装衬底的堆叠的多个导电通孔。

公开(公告)号：US20150221612A1

公开(公告)日：2015-08-06

申请号：US14171169

申请日：2014-02-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/06102 ,  H01L2224/06519 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/00012

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

Abstract translation: 描述了通过在堆叠中的模具之间包括金属热垫来改善堆叠半导体管芯的散热的系统和方法。 在一个实施例中，热焊盘可以与半导体管芯直接接触。 半导体管芯堆叠的散热可以通过直接接触堆叠中的相邻硅管芯而不需要低导热材料（例如，钝化材料）的中间层的热焊盘的相对较高的热导率来改善。 在一些实施例中，可以通过具有热焊盘和凸块下金属化（UBM）结构的大致共面的顶表面来改善堆叠的制造产量。

公开(公告)号：US20140353815A1

公开(公告)日：2014-12-04

申请号：US14464410

申请日：2014-08-20

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05655 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract translation: 制造多模组件的方法，其包括在其上没有集成电路并且具有多个垂直堆叠的骰子的晶片片段，其上通过导电通孔，所得到的多骰子组件和包括这种多模组件的半导体器件电连接。 晶片段可以用作散热器，以增强在所得到的多模组件中从堆叠的骰子的热传递。 芯片堆叠在基底晶片上的晶片级制造，晶片段和管芯堆叠至少在至少外围封装之后被分割。

公开(公告)号：US20140017823A1

公开(公告)日：2014-01-16

申请号：US14029187

申请日：2013-09-17

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L21/56 ,  H01L21/66

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05655 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract translation: 制造多模组件的方法，其包括在其上没有集成电路并且具有多个垂直堆叠的骰子的晶片片段，其上通过导电通孔，所得到的多骰子组件和包括这种多模组件的半导体器件电连接。 晶片段可以用作散热器，以增强在所得到的多模组件中从堆叠的骰子的热传递。 芯片堆叠在基底晶片上的晶片级制造，晶片段和管芯堆叠至少在至少外围封装之后被分割。