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    MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE
    32.
    发明申请
    MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE 有权
    具有强大功能的阅读架构的内存阵列

    公开(公告)号：US20160086666A1

    公开(公告)日：2016-03-24

    申请号：US14961042

    申请日：2015-12-07

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C16/04 ,  G11C16/26

    CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26

    Abstract: Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

    Abstract translation: 各种实施例包括具有上弦和下弦的三维存储装置的装置和方法。 上部串可以包括第一串存储器单元和基本上平行并彼此相邻布置的第二存储单元串。 较低的串可以包括第三串存储器单元和基本上平行并彼此相邻布置的第四串存储单元。 串可以各自具有耦合到其上的单独的读出放大器。 第一和第三串以及第二和第四串可以被配置为在读取操作期间彼此串联耦合。 描述附加的装置和方法。

    Apparatuses and methods including memory with top and bottom data lines
    34.
    发明授权
    Apparatuses and methods including memory with top and bottom data lines 有权
    装置和方法，包括具有顶部和底部数据线的存储器

    公开(公告)号：US09177614B2

    公开(公告)日：2015-11-03

    申请号：US14444589

    申请日：2014-07-28

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C5/06 ,  G11C5/02 ,  H01L27/115

    CPC classification number: G11C5/063 ,  G11C5/025 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.

    Abstract translation: 一些实施例包括具有第一组数据线，第二组数据线以及位于该装置的不同级别的存储单元的装置和方法。 在这样的实施例中的至少一个中，存储器单元可以被布置在第一和第二组数据线之间的存储单元串中。 描述包括附加装置和方法的其他实施例。

    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS
    35.
    发明申请
    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS 有权
    用于控制存储器操作中的身体潜力的装置和方法

    公开(公告)号：US20150287472A1

    公开(公告)日：2015-10-08

    申请号：US14746416

    申请日：2015-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

    IPC: G11C16/32 ,  G11C16/04

    CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

    Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

    APPARATUSES AND METHODS INCLUDING MEMORY ARRAY DATA LINE SELECTION
    36.
    发明申请
    APPARATUSES AND METHODS INCLUDING MEMORY ARRAY DATA LINE SELECTION 有权
    包括记忆阵列数据线选择的装置和方法

    公开(公告)号：US20150243364A1

    公开(公告)日：2015-08-27

    申请号：US14709210

    申请日：2015-05-11

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C16/26 ,  G11C16/04

    CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0483 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

    Abstract: Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. Other embodiments including additional apparatus and methods are described.

    Abstract translation: 一些实施例包括具有耦合到存储器单元串的数据线的装置和被配置为选择性地将数据线中的一个耦合到节点的选择器。 存储单元串和选择器可以形成在设备的相同存储器阵列中。 描述包括附加装置和方法的其它实施例。

    MEMORY READ APPARATUS AND METHODS
    37.
    发明申请
    MEMORY READ APPARATUS AND METHODS 有权
    内存读取装置和方法

    公开(公告)号：US20150179273A1

    公开(公告)日：2015-06-25

    申请号：US14639807

    申请日：2015-03-05

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C16/26 ,  G11C16/32 ,  G11C16/04

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/32

    Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.

    Abstract translation: 公开了一种装置和方法，其包括将多条接入线路的电位提升到升高的电位的方法，其中每条接入线路与一串电荷存储装置的相应电荷存储装置相关联。 所选择的一条接入线的电位降低，并且在所选择的接入线的电位降低的同时，感测与所选择的接入线相关联的电荷存储装置的数据状态。 描述附加的装置和方法。

    THREE-DIMENSIONAL DEVICES HAVING REDUCED CONTACT LENGTH
    38.
    发明申请
    THREE-DIMENSIONAL DEVICES HAVING REDUCED CONTACT LENGTH 有权
    具有减少接触长度的三维装置

    公开(公告)号：US20150155298A1

    公开(公告)日：2015-06-04

    申请号：US14615830

    申请日：2015-02-06

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: H01L27/115

    CPC classification number: H01L27/108 ,  H01L21/74 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

    Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed starting adjacent to a surface of a substrate. Peripheral circuitry is formed on an elevated portion that is adjacent to the memory array and has an uppermost portion substantially coplanar with an uppermost surface of the memory array. Additional apparatuses and methods are described.

    Abstract translation: 各种实施例包括装置和方法，包括具有交替电平的半导体材料和电介质材料的存储器阵列，其具有在交替电平上形成的存储器单元串。 一种这样的装置包括从衬底表面开始形成的存储器阵列。 外围电路形成在与存储器阵列相邻的升高部分上，并且具有与存储器阵列的最上表面基本共面的最上部分。 描述附加的装置和方法。

    Biasing system and method
    40.
    发明授权
    Biasing system and method 有权
    偏置系统和方法

    公开(公告)号：US09019766B2

    公开(公告)日：2015-04-28

    申请号：US14103560

    申请日：2013-12-11

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C16/04 ,  G11C16/30 ,  G11C16/10

    CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/10

    Abstract: Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system is in a non-operation state. The access device is selected when the memory system is in the non-operation state, and the access device is deselected when the memory system is in an other state. Further embodiments provide, for example, a method that includes coupling a global access line to a local access line, biasing the local access line to a voltage other than a negative supply voltage while a memory device is in a first state and uncoupling the global access line from the local access line while the memory device is in an other state.

    Abstract translation: 提供了实施例，其包括存储器系统，其包括存储器系统，其具有耦合在全局线路和本地线路之间的接入设备和耦合到全局线路的电压源，并且被配置为当存储器在全局线路上输出偏置电压 系统处于非操作状态。 当存储器系统处于非操作状态时，选择访问设备，并且当存储器系统处于其他状态时，访问设备被取消选择。 另外的实施例提供了一种方法，其包括将全局访问线耦合到本地访问线路，在存储器设备处于第一状态时将本地访问线路偏压到不同于负电源电压的电压，并且解除全局访问 当存储器设备处于另一状态时，从本地访问线路线。

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