公开(公告)号：US20110024827A1

公开(公告)日：2011-02-03

申请号：US12904231

申请日：2010-10-14

申请人： Fumitaka ARAI ,  Ichiro Mizushima ,  Makoto Mizukami

发明人： Fumitaka ARAI ,  Ichiro Mizushima ,  Makoto Mizukami

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42348 ,  H01L29/792

摘要： A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括：在其表面具有SOI区域和外延区域的半导体衬底，设置在SOI区域中的半导体衬底上的掩埋氧化膜，布置在掩埋氧化物上的SOI层 膜，布置在SOI层上的多个存储单元，布置在外延区中的外延层和布置在外延层上的选择栅极晶体管，其中SOI层由微晶层制成。

公开(公告)号：US07855457B2

公开(公告)日：2010-12-21

申请号：US12163145

申请日：2008-06-27

申请人： Makoto Mizukami ,  Takeshi Kamigaichi

发明人： Makoto Mizukami ,  Takeshi Kamigaichi

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/0217 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/06 ,  H01L2924/0002 ,  Y10T156/1057 ,  H01L2924/00

摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

摘要翻译： 根据本发明实施例的叠层多层结构包括：堆叠层部分，包括多个导电层和多个绝缘层，所述多个绝缘层与所述多个导电层的每个层交替叠层，一个 所述多个绝缘层是所述多个导电层和所述多个绝缘层中的最上层; 和多个触点，所述多个触点的每个触点由所述最顶层形成，并且所述多个触点的每个触点与所述多个导电层的相应导电层接触，所述多个触点的每一个的侧表面 的触点经由绝缘膜与所述多个导电层绝缘。

公开(公告)号：US20100159657A1

公开(公告)日：2010-06-24

申请号：US12715964

申请日：2010-03-02

申请人： Fumitaka ARAI ,  Riichiro Shirota ,  Makoto Mizukami

发明人： Fumitaka ARAI ,  Riichiro Shirota ,  Makoto Mizukami

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained; pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

摘要翻译： 半导体存储器件包括：在单元阵列区域中形成有杂质扩散层的半导体衬底; 形成在电池阵列区域上的栅极布线堆叠体，其中多个栅极布线彼此堆叠并且用绝缘膜分离; 形成在栅极布线堆叠体的侧表面上的栅极绝缘膜，其中包含绝缘电荷存储层; 沿着栅极布线堆叠体排列的柱状半导体层，其一个侧表面经由栅极绝缘膜与栅极布线堆叠体相对，每个柱状半导体层具有与杂质扩散层相同的导电类型; 以及形成为与柱状半导体层的上表面接触并与栅极布线相交的数据线。

公开(公告)号：US20100133627A1

公开(公告)日：2010-06-03

申请号：US12603099

申请日：2009-10-21

申请人： Makoto Mizukami ,  Kiyohito Nishihara

发明人： Makoto Mizukami ,  Kiyohito Nishihara

IPC分类号： H01L27/088

CPC分类号： H01L27/11568 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203

摘要： A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.

摘要翻译： 耗尽型NAND闪存包括由多个串联连接的FET组成的NAND串，控制电路，其在读取操作中控制多个FET的栅极电位，特定的电位存储器和相邻的存储单元阈值存储器， 其中，所述多个FET中的每一个是其阈值根据电荷累积层中的电荷量而变化的晶体管，所述相邻存储单元阈值存储器存储与所选择的FET的源极侧相邻的源极侧FET的阈值 ，并且控制电路在读取操作中向源极侧FET的栅电极施加电位，所施加的电位通过将存储在特定电位存储器中的特定电位加到存储在相​​邻存储单元阈值存储器中的阈值 。

公开(公告)号：US20080073695A1

公开(公告)日：2008-03-27

申请号：US11841257

申请日：2007-08-20

申请人： Makoto Mizukami ,  Riichiro Shirota ,  Fumitaka Arai

发明人： Makoto Mizukami ,  Riichiro Shirota ,  Fumitaka Arai

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/11524 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203

摘要： A semiconductor memory including a plurality of cell units arranged in a row direction, each of the cell units includes: a semiconductor region; a first buried insulating film provided on the semiconductor region; a second buried insulating film provided on the first buried insulating film, which has higher dielectric constant than the first buried insulating film; a semiconductor layer provided on the second buried insulating film; and a plurality of memory cell transistors arranged in a column direction, each of the memory cell transistors having a source region, a drain region and a channel region defined in the semiconductor layer.

摘要翻译： 一种半导体存储器，包括沿行方向布置的多个单元单元，每个单元单元包括：半导体区域; 设置在半导体区域上的第一掩埋绝缘膜; 设置在第一掩埋绝缘膜上的第二掩埋绝缘膜，其具有比第一掩埋绝缘膜更高的介电常数; 设置在所述第二掩埋绝缘膜上的半导体层; 以及沿列方向布置的多个存储单元晶体管，每个存储单元晶体管具有限定在半导体层中的源极区，漏极区和沟道区。

公开(公告)号：US06479257B1

公开(公告)日：2002-11-12

申请号：US09405085

申请日：1999-09-27

申请人： Akira Miyauchi ,  Makoto Ozawa ,  Masato Yoshida ,  Makoto Mizukami

发明人： Akira Miyauchi ,  Makoto Ozawa ,  Masato Yoshida ,  Makoto Mizukami

IPC分类号： C12P2106

CPC分类号： C07K1/1133 ,  C07K1/1136

摘要： The present invention relates to a method for activating protein wherein protein produced in a biologically inactive form (non-natural-form protein) is converted into a biologically active protein (natural-form protein) by bringing it into contact with cultured cells of an organism, and according to the present invention, the non-natural-form protein can be converted efficiently into the natural-form protein having activity, so the yield of the natural-form protein can be further raised by subjecting, e.g., culture of transformant to the activation treatment.

摘要翻译： 本发明涉及一种活化蛋白质的方法，其中以生物活性形式生成的蛋白质（非天然形式蛋白质）通过使其与生物体的培养细胞接触而转化为生物活性蛋白质（天然形式蛋白质） ，根据本发明，可以将非天然形式的蛋白质有效地转化为具有活性的天然形式的蛋白质，因此可以通过使转化体培养成 激活治疗。

公开(公告)号：US5413873A

公开(公告)日：1995-05-09

申请号：US96850

申请日：1993-07-26

申请人： Makoto Mizukami

发明人： Makoto Mizukami

IPC分类号： G11B5/73 ,  G11B5/00

CPC分类号： G11B5/7325 ,  Y10T428/12465 ,  Y10T428/12819 ,  Y10T428/12826 ,  Y10T428/12833 ,  Y10T428/12847 ,  Y10T428/12854 ,  Y10T428/12993 ,  Y10T428/24975 ,  Y10T428/265 ,  Y10T428/30 ,  Y10T428/31678

摘要： A magnetic recording medium comprising:a precoat layer, having a thickness of 30 to 14000 .ANG., consisting of any of V (vanadium), Mo (molybdenum), NiP (nickel-phosphorus), C (carbon), Zr (zirconium) or Al (aluminum) formed on a non-magnetic, mirror-surface substrate 1, anda Cr (chromium) layer as a primer layer 3 and a Co (cobalt) alloy layer as a magnetic layer 4 laminated in order on the precoat layer 2.

摘要翻译： 一种磁记录介质，包括：预涂层，其厚度为30至14000埃，由V（钒），Mo（钼），NiP（镍 - 磷），C（碳），Zr（锆）或 形成在非磁性镜面基板1上的Al（铝）和作为底涂层3的Cr（铬）层和作为磁性层4的Co（钴）合金层依次层叠在预涂层2上 。

公开(公告)号：US5024903A

公开(公告)日：1991-06-18

申请号：US331790

申请日：1989-04-03

申请人： Makoto Mizukami

发明人： Makoto Mizukami

IPC分类号： G11B5/66 ,  G11B5/64 ,  G11B5/706 ,  G11B5/73 ,  G11B5/738

CPC分类号： G11B5/656 ,  Y10S428/90 ,  Y10S428/928 ,  Y10T428/12465 ,  Y10T428/12861 ,  Y10T428/12875 ,  Y10T428/12931

摘要： A magnetic recording medium which comprises a non-magnetic substrate, a Cr undercoat layer formed on the substrate, and a quaternary alloy layer formed on the undercoat layer. The alloy layer consists of the following composition by atomic percent1.ltoreq.Cr.ltoreq.182.ltoreq.Ta.ltoreq.973.ltoreq.Co.ltoreq.971.ltoreq.Pt.ltoreq.10provided that the atomic percent of Cr, Ta and Co is 100 in total and the atomic percent of Pt is based on the total of Cr, Ta and Co.

摘要翻译： 一种磁记录介质，包括非磁性基板，形成在基板上的Cr底涂层和形成在底涂层上的四元合金层。 合金层由以下原子百分比组成的组成按照原子百分比1 = / / / / / / / = Cr，Ta和Co的原子百分数总计为100，Pt的原子百分比为Cr，Ta和Co的总和。

公开(公告)号：US08835934B2

公开(公告)日：2014-09-16

申请号：US13414394

申请日：2012-03-07

申请人： Makoto Mizukami

发明人： Makoto Mizukami

IPC分类号： H01L29/78 ,  H01L29/47 ,  H01L29/161 ,  H01L29/16 ,  H01L27/098 ,  H01L27/07 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06

CPC分类号： H01L27/0727 ,  H01L27/098 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/7806

摘要： A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.

摘要翻译： 半导体器件包括第一导电型半导体衬底，第一导电型半导体淀积层，沟槽，第二导电型阱，JFET区，第一导电型第一源极区，第一源极区，沟槽型源电极 栅极绝缘膜，栅电极和漏电极。 沟槽基本上垂直于半导体淀积层形成，使得半导体沉积层暴露于沟槽的底部。 第二导电类型的第二源极区域形成在第一导电型第一源极区域中。 沟槽型源电极与第一源极区域，第二源极区域和第一导电型半导体沉积层接触以构成肖特基结。

公开(公告)号：US20120223333A1

公开(公告)日：2012-09-06

申请号：US13220107

申请日：2011-08-29

申请人： Makoto Mizukami

发明人： Makoto Mizukami

IPC分类号： H01L29/06 ,  H01L29/161

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/43 ,  H01L29/6606

摘要： A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm3 and 5E+16 atoms/cm3 inclusive, and a thickness thereof is 8 μm or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 μm or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.

摘要翻译： 根据实施例的半导体整流器件包括宽半沟道半导体的第一导电类型的半导体衬底，形成在半导体衬底的上表面上的宽间隙半导体的第一导电类型的半导体层，其中杂质浓度 的半导体层的厚度为8μm以上，形成在半导体层上的第一导电类型的宽间隙半导体的第一半导体区域 形成为由所述第一半导体区域夹持的宽间隙半导体的第二导电类型的第二半导体区域，其中所述第二半导体区域的宽度为15μm以上，形成在所述第一半导体区域和所述第二半导体区域上的第一电极 ，以及形成在半导体基板的下表面上的第二电极。