公开(公告)号：US20160005815A1

公开(公告)日：2016-01-07

申请号：US14853793

申请日：2015-09-14

Applicant: Micron Technology, Inc.

Inventor： Chris Larsen ,  Alex J. Schrinsky ,  John D. Hopkins ,  Matthew J. King

IPC: H01L29/06

CPC classification number: H01L29/0657 ,  H01L21/743 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0692

Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.

Abstract translation: 一些实施例包括具有通过至少一个虚拟突起彼此间隔开的两个台面的半导体材料的半导体结构。 虚拟突起具有沿X的横截面的宽度，并且台面具有至少3X的横截面的宽度。 一些实施例包括具有存储器阵列区域和与存储器阵列区域相邻的外围区域的半导体结构。 周边区域内的半导体材料被图案化成两个相对较宽的台面，其彼此间隔开至少一个较窄的突起。 相对窄的突起具有沿X的横截面的宽度，并且相对宽的台面具有至少3X的横截面的宽度。

公开(公告)号：US12279423B2

公开(公告)日：2025-04-15

申请号：US17654028

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L21/768 ,  H01L27/11541 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11575 ,  H10B41/20 ,  H10B41/30 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20240074201A1

公开(公告)日：2024-02-29

申请号：US17893436

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Albert Fayrushin ,  Sidhartha Gupta ,  Jun Fujiki ,  Masashi Yoshida ,  Yiping Wang ,  Taehyun Kim ,  Arun Kumar Dhayalan

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. Conductive masses are formed that comprise at least one of conductively-doped semiconductive material or conductive metal material. Individual of the conductive masses are atop and directly electrically coupled to individual of the lower channel-material strings. Upper channel-material strings of select-gate transistors are formed directly above the stack. Individual of the upper channel-material strings are directly above and directly electrically coupled to individual of the conductive masses. Other embodiments, including structure, are disclosed.

公开(公告)号：US11910601B2

公开(公告)日：2024-02-20

申请号：US17141968

申请日：2021-01-05

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  John D. Hopkins ,  Matthew J. King ,  Roger W. Lindsay ,  Kevin Y. Titus

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/27

Abstract: A microelectronic device includes a pair of stack structures. The pair comprises a lower stack structure and an upper stack structure overlying the lower stack structure. The lower stack structure and the upper stack structure each comprise a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A source region is vertically interposed between the lower stack structure and the upper stack structure. A first array of pillars extends through the upper stack structure, from proximate the source region toward a first drain region above the upper stack structure. A second array of pillars extend through the lower stack structure, from proximate the source region toward a second drain region below the lower stack structure. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

公开(公告)号：US11756826B2

公开(公告)日：2023-09-12

申请号：US17473679

申请日：2021-09-13

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L21/768 ,  H01L21/762 ,  H10B43/40 ,  H10B43/20 ,  H10B43/35 ,  H10B43/50

CPC classification number: H01L21/76802 ,  H01L21/762 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76877 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

公开(公告)号：US20230043786A1

公开(公告)日：2023-02-09

申请号：US17966594

申请日：2022-10-14

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay ,  Christopher R. Ritchie ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11548 ,  G11C7/18

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials.

公开(公告)号：US11417681B2

公开(公告)日：2022-08-16

申请号：US17215308

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L27/115 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US11322516B2

公开(公告)日：2022-05-03

申请号：US17007951

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L27/11582 ,  H01L21/762 ,  H01L29/06

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

公开(公告)号：US20220059566A1

公开(公告)日：2022-02-24

申请号：US17516867

申请日：2021-11-02

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11519 ,  H01L21/3213 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Intervening material is formed into the stack laterally-between and longitudinally-along immediately-laterally-adjacent memory block regions. The forming of the intervening material comprises forming pillars laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. The pillars individually extend through multiple of each of the first tiers and the second tiers. After forming the pillars, an intervening opening is formed individually alongside and between immediately-longitudinally-adjacent of the pillars. Fill material is formed in the intervening openings. Other embodiments, including structure, are disclosed.

公开(公告)号：US20210408029A1

公开(公告)日：2021-12-30

申请号：US17473679

申请日：2021-09-13

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/11573 ,  H01L21/762 ,  H01L27/11578 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/11575

Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.