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41 条记录 (耗时 0.052 秒)

    Method for reworking low-k dual damascene photo resist
    36.
    发明申请
    Method for reworking low-k dual damascene photo resist 审中-公开
    低k双重镶嵌光刻胶修复方法

    公开(公告)号：US20070004193A1

    公开(公告)日：2007-01-04

    申请号：US11173275

    申请日：2005-07-01

    申请人： Tsang-Jiuh Wu ,  Chen-Nan Yeh ,  Dean Li ,  Hui Ouyang

    发明人： Tsang-Jiuh Wu ,  Chen-Nan Yeh ,  Dean Li ,  Hui Ouyang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808

    摘要： A new method of forming a dual damascene structure involves forming a via-level precursor structure on a substrate and spin coating an oxide protective layer over the bottom anti-reflective coating, which is the last layer of the via-level precursor structure. A trench-level photoresist layer is deposited over the oxide protective layer to form a trench pattern etch mask. The oxide protective layer protects the BARC layer and the via plugs from photoresist removing process. When and if the trench-level photoresist layer is to be reworked, the trench-level photoresist layer is simply removed without removing the BARC layer and the via plugs under the oxide protective layer.

    摘要翻译： 形成双镶嵌结构的新方法包括在基底上形成通孔级前体结构，并在作为通孔级前体结构的最后一层的底部抗反射涂层上旋转涂覆氧化物保护层。 沟槽级光致抗蚀剂层沉积在氧化物保护层上以形成沟槽图案蚀刻掩模。 氧化物保护层保护BARC层和通孔插塞免受光致抗蚀剂的去除。 当沟槽层光致抗蚀剂层要被再加工时，沟槽层光致抗蚀剂层被简单地去除，而不去除氧化物保护层下的BARC层和通孔塞。

    Source and drain feature profile for improving device performance
    38.
    发明授权
    Source and drain feature profile for improving device performance 有权
    源和漏功能配置文件，用于提高设备性能

    公开(公告)号：US08445940B2

    公开(公告)日：2013-05-21

    申请号：US13543943

    申请日：2012-07-09

    申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

    发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

    IPC分类号： H01L31/072

    CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

    摘要： An integrated circuit device is disclosed. The disclosed device provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device disclosed herein has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a {100} crystallographic plane of the substrate.

    摘要翻译： 公开了一种集成电路器件。 所公开的装置提供对集成电路装置的表面接近度和尖端深度的改进的控制。 本文公开的示例性集成电路器件具有约1nm至约3nm的表面接近度和约5nm至约10nm的尖端深度。 具有这种表面接近度和尖端深度的集成电路器件包括由第一方向（例如衬底的{111}晶体平面）的第一方向上的第一面和第二小面限定的外延源特征和外延漏极特征， 以及在第二方向上的衬底的第三面，例如衬底的{100}晶面。

    INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME
    39.
    发明申请
    INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME 有权
    具有良好控制的表面接近度的集成电路装置及其制造方法

    公开(公告)号：US20120001238A1

    公开(公告)日：2012-01-05

    申请号：US12827344

    申请日：2010-06-30

    申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

    发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

    IPC分类号： H01L29/78 ,  H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

    摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device.

    摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过形成用作蚀刻停止的轻掺杂源极和漏极（LDD）区域来实现改进的控制。 LDD区域可以在蚀刻工艺期间用作蚀刻停止层，以在衬底中形成限定器件的源极和漏极区域的凹陷。

    METHODS FOR A GATE REPLACEMENT PROCESS
    40.
    发明申请
    METHODS FOR A GATE REPLACEMENT PROCESS 有权
    门更换过程的方法

    公开(公告)号：US20110081774A1

    公开(公告)日：2011-04-07

    申请号：US12575280

    申请日：2009-10-07

    申请人： Matt Yeh ,  Hui Ouyang ,  Da-Yuan Lee ,  Kuang Yuan Hsu ,  Hun-Jan Tao ,  Xiong-Fei Yu

    发明人： Matt Yeh ,  Hui Ouyang ,  Da-Yuan Lee ,  Kuang Yuan Hsu ,  Hun-Jan Tao ,  Xiong-Fei Yu

    IPC分类号： H01L21/28

    CPC分类号： H01L29/401 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66545

    摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.

    摘要翻译： 公开了一种制造半导体器件的方法。 在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。 在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。