公开(公告)号：US06518113B1

公开(公告)日：2003-02-11

申请号：US09776853

申请日：2001-02-06

申请人： Matthew S. Buynoski

发明人： Matthew S. Buynoski

IPC分类号： H01L218238

CPC分类号： H01L21/823842 ,  Y10S438/923

摘要： Work function control layers are provided in in-laid, metal gate electrode, Si-based MOS transistors and CMOS devices by a process which avoids deleterious dopant implantation processing resulting in damage to the thin gate insulator layer and undesirable doping of the underlying channel region. According to the invention, an amorphous Si layer is formed over the thin gate insulator layer by a low energy deposition process which does not adversely affect the gate insulator layer and subsequently doped by means of another low energy process, e.g., low sheath voltage plasma doping, which does not damage the gate insulator layer or dope the underlying channel region of the Si-based substrate. Subsequent thermal processing during device manufacture results in activation of the dopant species and conversion of the a-Si layer to a doped polycrystalline Si layer of substantially increased electrical conductivity.

摘要翻译： 工作功能控制层通过一种避免有害的掺杂剂注入处理导致薄栅极绝缘体层的损坏和对下面的沟道区的不期望的掺杂的过程提供在嵌入式金属栅电极，Si基MOS晶体管和CMOS器件中。 根据本发明，通过低能量沉积工艺在薄栅极绝缘体层上形成非晶Si层，该方法不会对栅极绝缘体层产生不​​利影响，并且随后通过另一种低能量工艺（例如，低鞘电压等离子体掺杂 ，其不损坏栅极绝缘体层或掺杂Si基衬底的下面的沟道区域。 在器件制造过程中随后的热处理导致掺杂剂物质的激活和a-Si层转变成具有显着增加的导电性的掺杂多晶Si层。

公开(公告)号：US06492249B2

公开(公告)日：2002-12-10

申请号：US09304129

申请日：1999-05-03

申请人： Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

发明人： Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

IPC分类号： H01L213205

CPC分类号： H01L21/76897 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/31658 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

摘要翻译： 制造具有浅源极和漏极延伸的晶体管的方法利用自对准接触。 漏极延伸部分通过接触区域和栅极结构之间的开口提供。 可以使用高K栅介电材料。 可以根据所公开的方法创建P-MOS和N-MOS晶体管。

公开(公告)号：US06436840B1

公开(公告)日：2002-08-20

申请号：US09691188

申请日：2000-10-19

申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

IPC分类号： H01L21302

CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/3146 ,  H01L29/4941 ,  H01L29/517 ,  Y10S438/926

摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. A barrier is then deposited on the CVD amorphous silicon layer. A metal is then formed on the barrier. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer. The work function is preserved by the barrier during subsequent high temperature processing, due to the barrier which prevents interaction between the CVD amorphous silicon layer and the metal, which could otherwise form silicide and change the work function.

摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后在CVD非晶硅层上沉积阻挡层。 然后在屏障上形成金属。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。 由于防止CVD非晶硅层与金属之间的相互作用的屏障，因此在随后的高温处理期间，阻挡层保留功函数，否则可能形成硅化物并改变功函数。

公开(公告)号：US06248658B1

公开(公告)日：2001-06-19

申请号：US09229264

申请日：1999-01-13

申请人： Matthew S. Buynoski

发明人： Matthew S. Buynoski

IPC分类号： H01L214763

CPC分类号： G03F7/0042 ,  C23C16/047 ,  C23C18/08 ,  C23C18/14 ,  G03F7/16 ,  H01L21/288 ,  H01L21/32051

摘要： Submicron-dimensioned metallization patterns are formed on a substrate surface by a photolytic process wherein portions of a metal-compound containing fluid layer on the substrate surface which are exposed through a pattern of submicron-sized openings in an overlying exposure mask are irradiated with UV to near X-ray radiation. Photo-decomposition of the metal-containing compound results in selective metal deposition on the substrate surface according to the exposure mask pattern. When liquid, the fluid layer is prevented from contacting the mask surfaces during photolysis in order to prevent closing off of the very small apertures by deposition thereon. The inventive method is of particular utility in forming multi-level, in-laid, “back-end” metallization of high density integrated circuit semiconductor devices.

摘要翻译： 通过光解法在基底表面上形成亚微米尺寸的金属化图案，其中通过上覆曝光掩模中的亚微米尺寸开口的图案暴露在基底表面上的含有金属化合物的流体层的部分用UV照射 靠近X射线辐射。 含金属化合物的光分解根据曝光掩模图案导致在基板表面上的选择性金属沉积。 当液体时，在光解期间防止流体层与掩模表面接触，以防止通过沉积在非常小的孔上。 本发明的方法在形成高密度集成电路半导体器件的多层次的，内置的“后端”金属化中是特别有用的。

公开(公告)号：US06246118B1

公开(公告)日：2001-06-12

申请号：US09252185

申请日：1999-02-18

申请人： Matthew S. Buynoski

发明人： Matthew S. Buynoski

IPC分类号： H01L2348

CPC分类号： H01L23/5222 ,  H01L23/4821 ,  H01L24/05 ,  H01L2224/05093 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105

摘要： Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid, conductive lining, such as, a hard metal, e.g., W, Mo, Os, Ir or alloys thereof. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, electroplating or electroless plating the hard metal to line the interconnection system and forming dielectric protective layers, e.g., a silane derived oxide bottommost protective layer, on the uppermost metallization level.

摘要翻译： 多级半导体器件形成为具有减小的寄生电容，而不牺牲结构完整性或电迁移性能，通过去除层间电介质并用刚性导电衬里（例如W，Mo， Os，Ir或其合金。 实施例包括在形成第一金属化水平之前沉积电介质密封层，例如氮化硅，在形成最后金属化水平之后去除层间电介质，电镀或无电镀硬化金属以对互连系统进行排列并形成介电保护层 ，例如，硅烷衍生的氧化物最底层的保护层，最上层的金属化层。

公开(公告)号：US06187675B1

公开(公告)日：2001-02-13

申请号：US09325023

申请日：1999-06-03

申请人： Matthew S. Buynoski

发明人： Matthew S. Buynoski

IPC分类号： H01L2144

CPC分类号： H01L29/66507 ,  H01L21/28052 ,  H01L29/4933 ,  H01L29/66545 ,  H01L29/6659

摘要： The present invention is a method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the gate having low resistivity. The MOSFET has a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and the MOSFET initially has a gate comprised of a first metal silicide on polysilicon disposed on a gate dielectric over the channel region. Generally, the method of the present invention includes a step of depositing a first dielectric layer over the drain region, the source region, and the gate of the MOSFET. The present invention also includes steps of polishing down the first dielectric layer over the drain region and the source region, and of polishing down the first dielectric layer over the gate until the first metal silicide or the polysilicon of the gate is exposed. The present invention further includes the step of depositing a metal over the first metal silicide if the first metal silicide is exposed or over the polysilicon if the polysilicon is exposed, and of performing a silicidation anneal to form a second metal silicide over a remaining portion of the polysilicon. The thickness of the second metal silicide is a greater than the thickness of the first metal silicide. In this manner, the gate of the present invention has low resistivity since a relatively thick layer of metal silicide is formed on the remaining portion of the polysilicon. In addition, with the present invention, the remaining portion of the polysilicon has a sufficient thickness such that a threshold voltage of the MOSFET is not substantially affected by the second metal silicide disposed on top of the remaining portion of the polysilicon.

摘要翻译： 本发明是一种用于制造具有低电阻率的栅极的MOSFET（金属氧化物半导体场效应晶体管）的栅极的方法。 MOSFET具有在半导体衬底内制造的漏极区域，源极区域和沟道区域，MOSFET最初具有由沟道区域上的栅极电介质上的多晶硅上的第一金属硅化物构成的栅极。 通常，本发明的方法包括在MOSFET的漏极区域，源极区域和栅极之上沉积第一介电层的步骤。 本发明还包括在漏极区域和源极区域上抛光第一电介质层并且在栅极上抛光第一电介质层直到第一金属硅化物或栅极的多晶硅露出的步骤。 本发明还包括如果第一金属硅化物被暴露则在第一金属硅化物上沉积金属，如果多晶硅被暴露则沉积在多晶硅上，并且在剩余部分中进行硅化退火以形成第二金属硅化物的步骤 多晶硅。 第二金属硅化物的厚度大于第一金属硅化物的厚度。 以这种方式，本发明的栅极具有低电阻率，因为在多晶硅的剩余部分上形成了较厚的金属硅化物层。 此外，通过本发明，多晶硅的剩余部分具有足够的厚度，使得MOSFET的阈值电压基本上不受设置在多晶硅的剩余部分顶部的第二金属硅化物的影响。

公开(公告)号：US6078088A

公开(公告)日：2000-06-20

申请号：US225541

申请日：1999-01-05

申请人： Matthew S. Buynoski

发明人： Matthew S. Buynoski

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L29/76 ,  H01L29/00 ,  H01L29/94

CPC分类号： H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002

摘要： Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigation performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid lining. Embodiments include depositing a dielectric sealing layer, e.g., silicon oxide, silicon nitride or composite of silicon oxide/silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, lining the interconnection system with undoped polycrystalline silicon and forming a dielectric protective layer, e.g. a silane derived oxide, on the uppermost metallization level.

摘要翻译： 通过去除层间电介质并用刚性衬里支撑互连系统，多级半导体器件形成具有减小的寄生电容，而不牺牲结构完整性或电性能。 实施例包括在形成第一金属化水平之前沉积电介质密封层，例如氧化硅，氮化硅或氧化硅/氮化硅的复合物，在形成最后的金属化水平之后去除层间电介质，将未掺杂的互连系 多晶硅并形成介电保护层，例如 硅烷衍生的氧化物，位于最上层的金属化层。

公开(公告)号：US5932911A

公开(公告)日：1999-08-03

申请号：US766494

申请日：1996-12-13

申请人： John T. Yue ,  Matthew S. Buynoski ,  Yowjuang W. Liu ,  Peng Fang

发明人： John T. Yue ,  Matthew S. Buynoski ,  Yowjuang W. Liu ,  Peng Fang

IPC分类号： H01L21/265 ,  H01L21/335 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66636 ,  B82Y10/00 ,  H01L21/26586 ,  H01L29/41766 ,  H01L29/66439 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854

摘要： A field effect transistor is formed across one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

摘要翻译： 跨越一个或多个沟槽（26）或条（120）形成场效应晶体管，从而增加了沟道区的有效宽度和器件的载流能力。

公开(公告)号：US4999309A

公开(公告)日：1991-03-12

申请号：US553218

申请日：1990-07-12

申请人： Matthew S. Buynoski

发明人： Matthew S. Buynoski

IPC分类号： H01L27/04 ,  H01L21/225 ,  H01L21/266 ,  H01L21/329 ,  H01L21/331 ,  H01L21/822 ,  H01L29/73 ,  H01L29/732 ,  H01L29/93

CPC分类号： H01L21/26513 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/66174 ,  Y10S438/901

摘要： An improved process is described for the formation of PNP transistor collector base junctions or PN junction capaciters in silicon monolithic integrated circuits that employ the ion implantation and diffusion of aluminum in these regions that are to contain high performance PNP transistors or capacitors. The process reduces or eliminates the leakage typically found in such devices.

摘要翻译： 描述了一种改进的工艺，用于在硅单体集成电路中形成PNP晶体管集电极基极结或PN结电容，其中采用在包含高性能PNP晶体管或电容器的这些区域中的铝的离子注入和扩散。 该过程减少或消除了在这些设备中通常发现的泄漏。

公开(公告)号：US07432557B1

公开(公告)日：2008-10-07

申请号：US10755344

申请日：2004-01-13

申请人： Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

发明人： Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

IPC分类号： H01L23/62

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.

摘要翻译： 半导体器件包括源极区域，漏极区域和形成在源极区域和漏极区域之间的沟道组。 通道组中的至少一个通道通过氧化物结构与通道组中的另一个通道分离。 半导体器件还包括至少一个形成在该组沟道的至少一部分上的栅极。