公开(公告)号：US20160064067A1

公开(公告)日：2016-03-03

申请号：US14468976

申请日：2014-08-26

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/419 ,  H01L27/11 ,  H01L21/768 ,  H01L21/3213

CPC classification number: G11C11/419 ,  G11C7/18 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  G11C29/816 ,  H01L21/32133 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/1104

Abstract: An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (CPP) associated with the bit cell. For example, a bit cell may be a 3-port static random access memory (SRAM) bit cell that is compatible with self-aligned double patterning (SADP) processes and that can be manufactured using semiconductor manufacturing processes of less than 14 nanometers (nm).

Abstract translation: 一种装置包括第一读取端口，第二读取端口，写入端口和至少一个存储锁存器。 包括第一读取端口，第二读取端口和写入端口的位单元的宽度大于与位单元相关联的接触多边距（CPP）的两倍。 例如，位单元可以是与自对准双图案（SADP）工艺兼容的3端口静态随机存取存储器（SRAM）位单元，并且可以使用小于14纳米（nm）的半导体制造工艺来制造 ）。

公开(公告)号：US20160027726A1

公开(公告)日：2016-01-28

申请号：US14444104

申请日：2014-07-28

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Choh Fei Yeap ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/528 ,  H01L21/321 ,  H01L21/311 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer.

Abstract translation: 一种装置包括第一互连和第一屏障结构。 第一阻挡结构与电介质材料接触。 该装置还包括与第一阻挡结构和蚀刻停止层接触的第一保护结构。 至少部分地由第一保护结构和蚀刻停止层限定气隙。

公开(公告)号：US20150380080A1

公开(公告)日：2015-12-31

申请号：US14320024

申请日：2014-06-30

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang

IPC: G11C11/419 ,  G11C5/06

CPC classification number: G11C11/419 ,  G11C5/02 ,  G11C7/00 ,  G11C7/20 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417

Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

Abstract translation: 静态随机存取存储器（SRAM）存储单元包括一对交叉耦合的反相器和耦合到该对交叉耦合的反相器的第一反相器的第一节点的选通晶体管。 门控晶体管的栅极耦合到第一字线。 门控晶体管被配置为响应于第一字线信号而选择性地将位线耦合到第一逆变器的第一节点。 第一反相器具有耦合到第二字线的第二节点。 第一个字线和第二个字线都是独立可控的。

公开(公告)号：US20150255571A1

公开(公告)日：2015-09-10

申请号：US14341568

申请日：2014-07-25

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

Abstract translation: 在特定实施例中，一种方法包括在半导体器件的伪栅极上形成第一间隔结构，并在第一间隔物结构上形成牺牲隔离物。 该方法还包括蚀刻半导体器件的结构以形成开口，经由开口去除牺牲隔离物，以及沉积材料以限定间隙。

公开(公告)号：US20150076704A1

公开(公告)日：2015-03-19

申请号：US14026893

申请日：2013-09-13

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  John Jianhong Zhu

IPC: H01L23/522 ,  G06F17/50 ,  H01L21/768

CPC classification number: H01L21/76816 ,  G06F17/5068 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

Abstract translation: 在特定实施例中，一种方法包括形成与第一侧壁结构相邻并与半导体器件的心轴相邻的第二硬掩模层。 心轴的顶部在形成第二硬掩模层之前被暴露。 该方法还包括去除第一侧壁结构以暴露第一硬掩模层的第一部分。 该方法还包括蚀刻第一硬掩模层的第一部分以暴露电介质材料的第二部分。 该方法还包括蚀刻介电材料的第二部分以形成第一沟槽。 该方法还包括在第一沟槽内形成第一金属结构。

公开(公告)号：US10032678B2

公开(公告)日：2018-07-24

申请号：US15198763

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Da Yang ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L21/8234

Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

公开(公告)号：US20180114848A1

公开(公告)日：2018-04-26

申请号：US15839050

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US09953979B2

公开(公告)日：2018-04-24

申请号：US14673485

申请日：2015-03-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Junjing Bao ,  John Jianhong Zhu ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/76 ,  H01L21/70 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/768 ,  H01L21/285 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/285 ,  H01L21/76897 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.

公开(公告)号：US09922880B2

公开(公告)日：2018-03-20

申请号：US14498180

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Choh Fei Yeap

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/161 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/82345 ,  H01L21/02244 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/517

Abstract: A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.

公开(公告)号：US09799560B2

公开(公告)日：2017-10-24

申请号：US14853670

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  John Jianhong Zhu ,  Junjing Bao ,  Niladri Narayan Mojumder ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.