公开(公告)号：US20090091378A1

公开(公告)日：2009-04-09

申请号：US11869186

申请日：2007-10-09

Applicant: Anand Haridass ,  Colm B. O'Reilly ,  Roger D. Weekly

Inventor： Anand Haridass ,  Colm B. O'Reilly ,  Roger D. Weekly

IPC: H04B1/10

CPC classification number: G06F1/28

Abstract: A circuit and a method for detecting noise events in a system with time variable operating points is provided. A switched capacitor filter comprising a plurality of capacitor units, samples a first voltage to determine an average of a set of voltage measurements, forming an average voltage. A filter control unit controls the plurality of capacitor units in the switched capacitor filter. A comparing unit compares the average voltage to the first voltage to form a comparison. A signaling unit generates a signal to instruct circuits in a processor to initiate actions to keep the first voltage from drooping below a threshold level in response to the comparison.

Abstract translation: 提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路和方法。 一种开关电容滤波器，包括多个电容器单元，对第一电压进行采样，以确定一组电压测量的平均值，形成平均电压。 滤波器控制单元控制开关电容滤波器中的多个电容器单元。 比较单元将平均电压与第一电压进行比较以形成比较。 信号单元产生信号以指示处理器中的电路响应于比较而发起动作以使第一电压不会下降到低于阈值水平。

公开(公告)号：US07467050B2

公开(公告)日：2008-12-16

申请号：US11420825

申请日：2006-05-30

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

IPC: G06F1/26 ,  G06F11/30

CPC classification number: G06F1/305

Abstract: A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.

Abstract translation: 提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。 将经过时间平均的第一电压与第二电压进行比较。 生成信号以指示处理器内的电路以启动动作以使电压进一步下降。

公开(公告)号：US20080307282A1

公开(公告)日：2008-12-11

申请号：US11758708

申请日：2007-06-06

Applicant: Richard Dono ,  Roger D. Weekly

Inventor： Richard Dono ,  Roger D. Weekly

IPC: G06F11/25

CPC classification number: G01R31/318533

Abstract: A test card system for use in product development includes a device under test (DUT). The DUT comprises: a mount plane; a power input port coupled to the mount plane; a JTAG input port coupled to the mount plane; a clock signal distribution network coupled to the JTAG input port; a plurality of latches coupled to the clock signal distribution network and the power input port; and an output port coupled to the plurality of latches. A test card (TC) couples to the DUT, comprising: a JTAG interface coupled to the DUT JTAG input port and configured to provide test data to the DUT; a clock module coupled to the DUT clock signal distribution network and configured to generate a clock signal; and an analysis module coupled to the DUT output port and configured to receive data from the DUT.

Abstract translation: 用于产品开发的测试卡系统包括被测设备（DUT）。 DUT包括：安装平面; 耦合到所述安装平面的电力输入端口; 耦合到安装平面的JTAG输入端口; 耦合到JTAG输入端口的时钟信号分配网络; 耦合到时钟信号分配网络和电力输入端口的多个锁存器; 以及耦合到所述多个锁存器的输出端口。 测试卡（TC）耦合到DUT，包括：耦合到DUT JTAG输入端口并被配置为向DUT提供测试数据的JTAG接口; 时钟模块，其耦合到所述DUT时钟信号分配网络并且被配置为生成时钟信号; 以及耦合到DUT输出端口并被配置为从DUT接收数据的分析模块。

公开(公告)号：US20080224714A1

公开(公告)日：2008-09-18

申请号：US11685226

申请日：2007-03-13

Applicant: Tanit Virutchapunt ,  Sungjun Chun ,  Timothy M. Skergan ,  Roger D. Weekly

Inventor： Tanit Virutchapunt ,  Sungjun Chun ,  Timothy M. Skergan ,  Roger D. Weekly

IPC: G01R27/02

CPC classification number: G01R31/31922 ,  G01R27/02 ,  G01R31/31937

Abstract: A system and method of integrated circuit control for in situ impedance measurement including a system with a plurality of functional partitions in a clocked logic type integrated circuit, the functional partitions having a communication controller and a modulation gate, the modulation gate receiving a clock signal and a modulation signal and generating a modulated clock signal for the functional partition; at least one of the communication controllers receiving an in-band signal and selectively communicating the in-band signal to the other communication controllers; and at least one of the functional partitions having a modulator, the modulator receiving the clock signal and a modulation control signal and generating the modulation signal.

Abstract translation: 一种用于原位阻抗测量的集成电路控制的系统和方法，包括在时钟逻辑型集成电路中具有多个功能分区的系统，功能分区具有通信控制器和调制门，调制门接收时钟信号， 调制信号并产生用于功能分区的调制时钟信号; 所述通信控制器中的至少一个接收带内信号并选择性地将所述带内信号传送到所述其他通信控制器; 并且功能分区中的至少一个具有调制器，调制器接收时钟信号和调制控制信号并产生调制信号。

公开(公告)号：US07017139B2

公开(公告)日：2006-03-21

申请号：US10794294

申请日：2004-03-05

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/40

Abstract: A system for minimizing the length of the longest diagonal interconnection. A multiple chip module may comprise a first chip connected to a second chip located diagonally to the first chip. The first and second chip are interconnected by one or more interconnections commonly referred to as diagonal interconnections. Since the one or more diagonal interconnections between the first chip and the second chip are interconnected between a set of pins on each chip that form a triangular pattern, the longest diagonal interconnection is substantially the same length as the length of the longest orthogonal interconnection. Furthermore, since the one or more diagonal interconnections between the first chip and the second chip are interconnected between a set of pins on each chip that form a triangular pattern, the longest diagonal interconnection is substantially the same length as the length of the second longest diagonal interconnection.

公开(公告)号：US08958214B2

公开(公告)日：2015-02-17

申请号：US13611609

申请日：2012-09-12

Applicant: John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

Inventor： John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

IPC: H05K1/11 ,  H05K1/14 ,  G11C5/02 ,  H05K3/00 ,  H05K3/32

CPC classification number: H05K1/144 ,  G11C5/025 ,  H05K1/113 ,  H05K1/114 ,  H05K1/141 ,  H05K3/0058 ,  H05K3/325 ,  H05K2201/044 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10719 ,  H05K2201/2009

Abstract: Mechanisms for interconnecting and distributing signals and power between PCBs are provided. A first PCB having land grid arrays (LGAs) and a first wiring layer designed for interconnect components on the first PCB, and a second wiring layer for connecting the components to a second PCB, are provided. The second PCB has opposed parallel first and second surfaces, the first surface having a LGA. A wiring layer designed to interconnect components on the second PCB, and a layer for interconnecting the components on the second PCB with the components on the first PCB, are provided. A first interposer couples to a LGA of a first surface of the first PCB and connects a component to the first PCB. A second interposer is sandwiched between and couples to a LGA of a second surface of the first PCB and to the LGA of the first surface of the second PCB.

Abstract translation: 提供了在PCB之间互连和分配信号和电源的机制。 提供了具有平面栅格阵列（LGAs）的第一PCB和为第一PCB上的互连部件设计的第一布线层以及用于将部件连接到第二PCB的第二布线层。 第二PCB具有相对的平行的第一和第二表面，第一表面具有LGA。 设置用于互连第二PCB上的组件的布线层和用于将第二PCB上的组件与第一PCB上的组件互连的层。 第一插入器耦合到第一PCB的第一表面的LGA并将部件连接到第一PCB。 第二插入件夹在第一PCB的第二表面的LGA和第二PCB的第一表面的LGA之间并耦合到第二PCB的第二表面的LGA。

公开(公告)号：US08927879B2

公开(公告)日：2015-01-06

申请号：US12952152

申请日：2010-11-22

Applicant: Jinwoo Choi ,  Sungjun Chun ,  Jason L. Frankel ,  Paul R. Walling ,  Roger D. Weekly

Inventor： Jinwoo Choi ,  Sungjun Chun ,  Jason L. Frankel ,  Paul R. Walling ,  Roger D. Weekly

IPC: H05K1/11 ,  H05K3/02 ,  H05K1/02

CPC classification number: H05K1/0224 ,  G06F17/5081 ,  H05K1/116 ,  H05K2201/09681 ,  H05K2201/09718 ,  H05K2201/09727 ,  Y10T29/49004 ,  Y10T29/49155 ,  Y10T29/53022

Abstract: A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.

Abstract translation: 网格层的网格线段的第一选择是第一宽度，并且网格层的网格线段的第二选择具有第二宽度，其中第二宽度大于第一宽度。 第二宽度的网格线段的第二选择与信号层中可能引入串扰的信号线的选择平行地布置，其中遮蔽信号线选择的网线段的加宽增加了 与信号相关联的返回电流将在更宽的网格线段中流动，从而增加了包含与信号相关联的电磁场的可能性，使得与其他信号的串扰减少或包含。

公开(公告)号：US08446738B2

公开(公告)日：2013-05-21

申请号：US12579051

申请日：2009-10-14

Applicant: John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

Inventor： John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/144 ,  G11C5/025 ,  H05K1/113 ,  H05K1/114 ,  H05K1/141 ,  H05K3/0058 ,  H05K3/325 ,  H05K2201/044 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10719 ,  H05K2201/2009

Abstract: A system, method, and motherboard assembly are described for interconnecting and distributing signals and power between co-planar boards that function as a single motherboard. The motherboard assembly includes a multilayered first printed circuit board having opposed parallel first and second surfaces, each having at least one land grid array (LGA) disposed thereon. The assembly further includes at least one wiring layer (Y) designed to only electrically interconnect components on or within the first PCB, and at least one wiring layer (X) designed to only electrically connect the components on the first PCB to a multilayered second PCB. The multilayered second PCB has opposed parallel first and second surfaces, the first surface having at least one LGA disposed thereon. It further includes at least one wiring layer (V) designed to only electrically interconnect components on or within the second PCB, and at least one layer (X) designed to only electrically interconnect the components on the second PCB with the components on the first PCB. A first LGA interposer couples to the LGA disposed on the first surface of the first PCB, and electrically connects at least one component to the first PCB. A second LGA interposer is sandwiched between and couples to the LGA disposed on the second surface of the first PCB and to the LGA disposed on the first surface of the second PCB. It electrically connects the first PCB to components on the second PCB.

Abstract translation: 描述了用于在用作单个主板的共面板之间互连和分配信号和功率的系统，方法和主板组件。 主板组件包括具有相对的平行的第一和第二表面的多层第一印刷电路板，每个具有设置在其上的至少一个焊盘格栅阵列（LGA）。 组件还包括至少一个布线层（Y），其被设计成仅电连接第一PCB上或其内部的部件，以及至少一个布线层（X），其设计成仅将第一PCB上的部件电连接到多层第二PCB 。 所述多层第二PCB具有相对的平行的第一和第二表面，所述第一表面具有设置在其上的至少一个LGA。 它还包括至少一个被设计成仅电连接第二PCB上或第二PCB内的组件的布线层（V），以及设计成仅将第二PCB上的部件与第一PCB上的部件电互连的至少一个层（X） 。 第一LGA插入器耦合到布置在第一PCB的第一表面上的LGA，并且将至少一个部件电连接到第一PCB。 第二LGA插入件夹在布置在第一PCB的第二表面上的LGA之间并耦合到布置在第二PCB的第一表面上的LGA。 它将第一个PCB电连接到第二个PCB上的组件。

公开(公告)号：US20120331429A1

公开(公告)日：2012-12-27

申请号：US13603732

申请日：2012-09-05

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

公开(公告)号：US08214658B2

公开(公告)日：2012-07-03

申请号：US12194620

申请日：2008-08-20

Applicant: Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcolm S. Ware ,  Roger D. Weekly

Inventor： Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcolm S. Ware ,  Roger D. Weekly

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: Mitigating effects of delamination of components in the data processing system is provided. A signal is received from one or more sensors in the data processing system. A determination is made as to whether the signal indicates that one threshold in a plurality of thresholds has been reached or exceeded. Responsive to the signal indicating that one threshold in the plurality of thresholds has been reached or exceeded, a determination is made as to whether the one threshold is a low temperature threshold or a high temperature threshold. Responsive to the one threshold being a low temperature threshold, one of a plurality of actions is initiated to increase a temperature of the data processing system thereby mitigating effects of delamination of the components in the data processing system.

Abstract translation: 提供了数据处理系统中组件分层的缓解效应。 从数据处理系统中的一个或多个传感器接收信号。 确定信号是否指示已经达到或超过多个阈值中的一个阈值。 响应于指示已经达到或超过多个阈值中的一个阈值的信号，确定一个阈值是低温阈值还是高温阈值。 响应于一个阈值是低温阈值，开始多个动作之一以增加数据处理系统的温度，从而减轻数据处理系统中组件的分层影响。