公开(公告)号：US20170347456A1

公开(公告)日：2017-11-30

申请号：US15165813

申请日：2016-05-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yushuang YAO ,  Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Francis J. CARNEY ,  Yusheng LIN

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/09 ,  H05K3/34 ,  H05K1/03

CPC classification number: H05K1/181 ,  H01L23/48 ,  H05K1/0203 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/341 ,  H05K3/3431 ,  H05K3/3494 ,  H05K3/4015 ,  H05K2201/10189 ,  H05K2201/10257 ,  H05K2201/10333 ,  H05K2203/1316 ,  H05K2203/1327 ,  H05K2203/16

Abstract: A method, in some embodiments, comprises: providing a direct bonded copper (DBC) substrate including a plurality of copper traces; providing a guide plate having protrusions on a surface of the guide plate; mounting hollow bush rings onto the protrusions; mounting the bush rings onto the copper traces by aligning the protrusions of the guide plate with solder units on said copper traces; attaching the bush rings and one or more dies to the copper traces by simultaneously reflowing said solder units and other solder units positioned between the dies and the copper traces; and after said simultaneous reflow, removing the protrusions from the bush rings.

公开(公告)号：US20170345864A1

公开(公告)日：2017-11-30

申请号：US15168828

申请日：2016-05-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Larry KINSMAN ,  Yusheng LIN ,  Yu-Te HSIEH ,  Oswald SKEETE ,  Weng-Jin WU ,  Chi-Yao KUO

IPC: H01L27/146 ,  H01L21/56 ,  H01L23/498 ,  H04N5/374 ,  H01L21/48

CPC classification number: H01L27/14643 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/49816 ,  H01L23/49838 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/24 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/181 ,  H04N5/374 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

公开(公告)号：US20240203845A1

公开(公告)日：2024-06-20

申请号：US18592704

申请日：2024-03-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L23/40 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/367 ,  H01L23/4093 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/80 ,  H01L25/0657

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20240186285A1

公开(公告)日：2024-06-06

申请号：US18444221

申请日：2024-02-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Francis J. CARNEY ,  Chee Hiong CHEW ,  Shunsuke YASUDA

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L24/94 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/561 ,  H01L2021/60015 ,  H01L2224/94

Abstract: A method includes placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof, and placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer. The method further includes activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer, and singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block.

公开(公告)号：US20240128240A1

公开(公告)日：2024-04-18

申请号：US18398589

申请日：2023-12-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/071 ,  H01L23/367 ,  H01L24/32 ,  H01L25/50 ,  H01L2224/32245

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

公开(公告)号：US20220415858A1

公开(公告)日：2022-12-29

申请号：US17823164

申请日：2022-08-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L25/07 ,  H01L25/00 ,  H01L23/367 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

公开(公告)号：US20220415857A1

公开(公告)日：2022-12-29

申请号：US17823149

申请日：2022-08-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L25/07 ,  H01L25/00 ,  H01L23/367 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

公开(公告)号：US20220285267A1

公开(公告)日：2022-09-08

申请号：US17249436

申请日：2021-03-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Yusheng LIN

IPC: H01L23/522 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00

Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor die having a back side and a front side, the back side being coupled with a base, the front side including active circuitry. The assembly can include a first resin encapsulation layer disposed on a first portion of the front side. The first resin encapsulation layer can be patterned to define a first opening exposing a second portion of the front side through the first resin encapsulation layer. The assembly can include a signal distribution structure that is disposed on the first resin encapsulation layer, and electrically coupled with the front side through the first opening. The assembly can include a second resin encapsulation layer disposed on a first portion of the signal distribution structure, the second resin encapsulation layer being patterned to define a second opening that exposes a second portion of the signal distribution structure.

公开(公告)号：US20220131002A1

公开(公告)日：2022-04-28

申请号：US16949321

申请日：2020-10-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Yusheng LIN ,  Kazuo OKADA ,  Hideaki YOSHIMI ,  Shunsuke YASUDA

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/66

Abstract: According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area.

公开(公告)号：US20220020848A1

公开(公告)日：2022-01-20

申请号：US16948801

申请日：2020-10-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Gordon M. GRIVNA ,  Yusheng LIN

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/20 ,  H01L25/07

Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor substrate that excludes a buried oxide layer. The semiconductor device assembly can also include a first semiconductor device stack disposed on a first portion of the semiconductor substrate, and a second semiconductor device stack disposed on a second portion of the semiconductor substrate. The semiconductor device assembly can further include an isolation trench having a dielectric material disposed therein, the isolation trench being disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The isolation trench can electrically isolate the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.