公开(公告)号：US20110095429A1

公开(公告)日：2011-04-28

申请号：US12985570

申请日：2011-01-06

申请人： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

发明人： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

IPC分类号： H01L23/48 ,  H01L23/532

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

摘要： Methods for forming conductive vias include foiling one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof A barrier layer may be fowled over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

摘要翻译： 用于形成导电通孔的方法包括在基板中形成一个或多个通孔。 通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。 通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。阻挡层可以在每个通孔的表面上被覆盖。 可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。 还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

公开(公告)号：US07918383B2

公开(公告)日：2011-04-05

申请号：US11140420

申请日：2005-05-27

申请人： Kyle K. Kirby ,  Salman Akram ,  Daniel P. Cram ,  Roy T. Lange ,  Warren M. Farnworth

发明人： Kyle K. Kirby ,  Salman Akram ,  Daniel P. Cram ,  Roy T. Lange ,  Warren M. Farnworth

IPC分类号： B23K31/02

CPC分类号： B23K1/085 ,  B23K1/0016 ,  B23K3/0653 ,  B23K2101/40

摘要： Methods and devices for placing a semiconductor wafer or other substrate in contact with solder are described. A wave soldering apparatus includes a solder bath, a nozzle for producing a solder wave, and a jig for orienting a substrate in a substantially vertical orientation and placing the substrate in contact with a cascading solder wave. In another wave soldering apparatus, a jig orients a semiconductor wafer in a substantially horizontal orientation in contact with the solder wave. Another soldering apparatus includes a tank comprising molten solder and a fixture configured to orient one or more semiconductor wafers in a substantially vertical orientation. Methods of placing semiconductor wafers or other substrates in contact with solder using the devices of the present invention are also disclosed.

摘要翻译： 描述了将半导体晶片或其它基板与焊料接触的方法和装置。 波峰焊装置包括焊料槽，用于产生焊波的喷嘴和用于使基板垂直定向的夹具，并使基板与级联焊波接触。 在另一种波峰焊装置中，夹具使得与焊波接触的大致水平取向的半导体晶片。 另一个焊接装置包括一个包含熔融焊料和一个被配置为使一个或多个半导体晶片呈基本垂直取向取向的夹具的罐。 还公开了使用本发明的装置将半导体晶片或其它基板与焊料接触的方法。

公开(公告)号：US07892972B2

公开(公告)日：2011-02-22

申请号：US11347153

申请日：2006-02-03

申请人： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

发明人： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

摘要翻译： 用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。 通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。 通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。 可以在每个通孔的表面上形成阻挡层。 可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。 还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

公开(公告)号：US07858429B2

公开(公告)日：2010-12-28

申请号：US11863087

申请日：2007-09-27

申请人： Salman Akram ,  Charles M. Watkins ,  Kyle K. Kirby ,  Alan G. Wood ,  William M. Hiatt

发明人： Salman Akram ,  Charles M. Watkins ,  Kyle K. Kirby ,  Alan G. Wood ,  William M. Hiatt

IPC分类号： H01L21/00 ,  G02F1/13

CPC分类号： H01L27/146 ,  H01L21/76898 ,  H01L27/14618 ,  H01L27/148 ,  H01L31/02016 ,  H01L2224/48227 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/00

摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.

摘要翻译： 本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。 在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。 接合焊盘由衬底承载并电耦合到集成电路。 导电晶片互连延伸穿过衬底并与接合焊盘接触。 互连可以包括完全延伸穿过衬底和接合焊盘的通道，沉积到通道中并与衬底接触的电介质衬垫，沉积在电介质衬垫的至少一部分上的第一和第二导电层以及导电 在第二导电层的至少一部分上沉积到通道中并且电耦合到接合焊盘的填充材料。

公开(公告)号：US07791184B2

公开(公告)日：2010-09-07

申请号：US11411265

申请日：2006-04-26

申请人： Alan G. Wood ,  Kyle K. Kirby ,  Warren M. Farnworth ,  Salman Akram

发明人： Alan G. Wood ,  Kyle K. Kirby ,  Warren M. Farnworth ,  Salman Akram

IPC分类号： H01L23/02

CPC分类号： H01L27/14618 ,  B33Y80/00 ,  H01L27/14625 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.

摘要翻译： 诸如图像传感器封装的半导体封装。 框架结构包括每个具有穿过其中的孔的框架阵列，图像传感器与盖玻片，过滤器，透镜或其它部件组合的模具可以精确地相互对准地安装在该框架中。 单片图像传感器骰子和其他组件可以被拾取并放置在框架结构的每个帧中。 或者，框架结构可以被配置为与承载多个图像传感器骰子的晶片对准并且连接到其上，其中沿着框架的周边的任选的向下突出的裙边可以被接收到沿着晶片上的模具位置之间沿着街道切割的切口 ，然后安装其他包装组件。 在任一情况下，将帧结构与单独的图像传感器芯片或连接的晶片组合成单独的图像传感器封装。 可以使用各种外部连接方法。

公开(公告)号：US07683458B2

公开(公告)日：2010-03-23

申请号：US11924781

申请日：2007-10-26

申请人： Salman Akram ,  Charles M. Watkins ,  William M. Hiatt ,  David R. Hembree ,  James M. Wark ,  Warren M. Farnworth ,  Mark E. Tuttle ,  Sidney B. Rigg ,  Steven D. Oliver ,  Kyle K. Kirby ,  Alan G. Wood ,  Lu Velicky

发明人： Salman Akram ,  Charles M. Watkins ,  William M. Hiatt ,  David R. Hembree ,  James M. Wark ,  Warren M. Farnworth ,  Mark E. Tuttle ,  Sidney B. Rigg ,  Steven D. Oliver ,  Kyle K. Kirby ,  Alan G. Wood ,  Lu Velicky

IPC分类号： H01L23/485

CPC分类号： H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

摘要翻译： 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

公开(公告)号：US20090309176A1

公开(公告)日：2009-12-17

申请号：US12139068

申请日：2008-06-13

申请人： Salman Akram ,  Kyle K. Kirby

发明人： Salman Akram ,  Kyle K. Kirby

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L27/14618 ,  H01L27/14636 ,  H01L27/14685 ,  H01L2224/13

摘要： Methods for processing photoimagers include forming one or more protective layers over the image sensing elements of a photoimager. Protective layers may facilitate thinning of the substrates of photoimagers, as well as prevent contamination of the image sensing elements and associated optical features during back side processing of the photoimagers. Blind vias, which extend from the back side of a photoimager to bond pads carried by an active surface of the photoimager, may be formed through the back side. The vias may be filled with conductive material and, optionally, redistribution circuitry may be fabricated over the back side of the photoimager. Photoimagers including features at result from such processes are also disclosed.

摘要翻译： 用于处理光影目标的方法包括在光成像仪的图像感测元件上形成一个或多个保护层。 保护层可以促进光刻胶的基材的变薄，并且可以防止在光成像器的背面处理期间图像感测元件和相关的光学特征的污染。 可以通过背面形成从光电成像仪的背面延伸到由光电成像仪的有源表面承载的接合焊盘的盲通孔。 通孔可以用导电材料填充，并且可选地，重新分布电路可以在光电成像仪的背面上制造。 还公开了包括这些处理结果的特征的光照器。

公开(公告)号：US20090191701A1

公开(公告)日：2009-07-30

申请号：US12419029

申请日：2009-04-06

申请人： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

发明人： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

摘要翻译： 本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。 在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。 衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。 该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。 该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。 该方法然后包括用导电材料填充通道。

公开(公告)号：US20080290435A1

公开(公告)日：2008-11-27

申请号：US11751206

申请日：2007-05-21

申请人： Steve Oliver ,  Kyle K. Kirby ,  Warren M. Farnworth ,  William M. Hiatt ,  Salman Akram

发明人： Steve Oliver ,  Kyle K. Kirby ,  Warren M. Farnworth ,  William M. Hiatt ,  Salman Akram

IPC分类号： H01L31/0232 ,  B29D11/00 ,  H01L21/00

CPC分类号： B29D11/00375 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14632 ,  H01L27/14685 ,  H01L2924/0002 ,  H01L2924/00

摘要： Image sensor packages, lenses therefore, and methods for fabrication are disclosed. A substrate having through-hole vias may be provided, and an array of lenses may be formed in the vias. The lenses may be formed by molding or by tenting material over the vias. An array of lenses may provide a color filter array (CFA). Filters of the CFA may be formed in the vias, and lenses may be formed in or over the vias on either side of the filters. A substrate may include an array of microlenses, and each microlens of the array may correspond to a pixel of an associated image sensor. In other embodiments, each lens of the array may correspond to an imager array of an image sensor. A wafer having an array of lenses may be aligned with and attached to an imager wafer comprising a plurality of image sensor dice, then singulated to form a plurality of image sensor packages.

摘要翻译： 公开了图像传感器封装，透镜以及制造方法。 可以提供具有通孔过孔的衬底，并且可以在通孔中形成透镜阵列。 透镜可以通过模制或通过在通孔上的材料的凸起来形成。 透镜阵列可以提供滤色器阵列（CFA）。 可以在过孔中形成CFA的过滤器，并且透镜可以形成在过滤器两侧的通孔中或上方。 衬底可以包括微透镜阵列，并且阵列的每个微透镜可以对应于相关联的图像传感器的像素。 在其他实施例中，阵列的每个透镜可以对应于图像传感器的成像器阵列。 具有透镜阵列的晶片可以与包括多个图像传感器芯片的成像器晶片对准并且附接到成像器晶片，然后被单个化以形成多个图像传感器封装。

公开(公告)号：US07329943B2

公开(公告)日：2008-02-12

申请号：US11416824

申请日：2006-05-03

申请人： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

发明人： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

IPC分类号： H01L29/40

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

摘要翻译： 本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。 在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。 衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。 该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。 该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。 该方法然后包括用导电材料填充通道。