公开(公告)号：US10424490B2

公开(公告)日：2019-09-24

申请号：US15805848

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon Kim ,  Minsu Seol ,  Hyeonjin Shin ,  Dongwook Lee ,  Seongjun Jeong

IPC: H01L21/308 ,  C09D1/00 ,  C08K3/04 ,  C08K9/04 ,  G03F7/20 ,  G03F7/32 ,  G03F7/40 ,  C09D7/62 ,  C09D7/40 ,  C01B32/15 ,  C01B32/152 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  C01B32/184 ,  C01B32/156 ,  G03F7/09

Abstract: Provided are a hardmask composition and a method of forming a fine pattern using the hardmask composition, the hardmask composition including a solvent, a 2D carbon nanostructure (and/or a derivative thereof), and a 0D carbon nanostructure (and/or a derivative thereof).

公开(公告)号：US20170271154A1

公开(公告)日：2017-09-21

申请号：US15611935

申请日：2017-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin SHIN ,  Sangwon Kim ,  Seongjun Park

IPC: H01L21/033 ,  C08K3/38 ,  G03F7/09 ,  C08K3/30 ,  C08K5/56 ,  C08K3/22 ,  H01L21/311 ,  C09D7/12

CPC classification number: H01L21/0332 ,  C08K3/22 ,  C08K3/30 ,  C08K3/38 ,  C08K5/56 ,  C08K2003/2255 ,  C08K2003/3009 ,  C08K2003/385 ,  C09D7/61 ,  C09D7/63 ,  G03F7/094 ,  H01L21/02112 ,  H01L21/02282 ,  H01L21/0254 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/02584 ,  H01L21/02628 ,  H01L21/31122 ,  H01L21/31144

Abstract: Example embodiments relate to a hardmask composition and/or a method of forming a fine pattern by using the hardmask composition, wherein the hardmask composition includes at least one of a two-dimensional layered nanostructure and a precursor thereof, and a solvent, and an amount of the at least one of a two-dimensional layered nanostructure and the precursor is about 0.01 part to about 40 parts by weight based on 100 parts by weight of the hardmask composition.

公开(公告)号：US09099541B2

公开(公告)日：2015-08-04

申请号：US14170062

申请日：2014-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Sunpil Youn ,  Sangwon Kim ,  Kwang-chul Choi ,  Tae Hong Min

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a substrate having a first side and a second side such that the first and second sides face each other, a through via plug penetrating the substrate, an insulating film liner, and an antipollution film. The insulating film liner is between the through via plug and the substrate and the insulating film liner has a recessed surface with respect to the second side. The antipollution film covers the second side and the antipollution film is on the recessed surface and between the through via plug and the substrate.

Abstract translation: 半导体器件包括具有第一侧和第二侧的基板，使得第一和第二面彼此面对，贯穿基板的通孔塞，绝缘膜衬垫和防污染膜。 绝缘膜衬垫位于通孔插塞和衬底之间，并且绝缘膜衬套相对于第二侧具有凹陷表面。 防污染膜覆盖第二面，防污染膜位于凹陷表面上，并且在通孔插塞和基底之间。

公开(公告)号：USRE50395E1

公开(公告)日：2025-04-22

申请号：US17750154

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwon Kim ,  Youngkook Kim ,  Jeongryeol Seo ,  Hyewon Lee

IPC: G06F3/14 ,  G09G3/32

Abstract: An electronic apparatus includes an interface connected to a modular display apparatus, and a processor for transmitting an image signal to the modular display apparatus connected through the interface. The processor divides a plurality of display modules included in the modular display apparatus into a plurality of groups based on a vertical direction, divides the image signal into a plurality of image signals corresponding to the plurality of groups, and transmits the divided plurality of image signals to the plurality of groups.

公开(公告)号：US12284794B2

公开(公告)日：2025-04-22

申请号：US18359208

申请日：2023-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonggeun Yoon ,  Sangwon Kim ,  Youngwook Kim ,  Chankyu Lim ,  Pilwon Seo ,  Jiwoo Lee

IPC: H05K7/20 ,  G06F3/0354 ,  G06F3/038 ,  G09G3/20

Abstract: An electronic device including a thermal diffusion member for reducing hot spots is provided. The electronic device includes a plurality of display driver integrated circuits (DDICs) spaced apart from each other in a non-display area of a display panel, and disposed oriented in a first direction from the display panel, a circuit board disposed in a second direction opposite to the first direction from the display panel, and including a timing controller IC (T-CON IC) disposed so as to overlap at least some of the plurality of DDICs when the display panel is viewed from the first direction, a flexible circuit board disposed at one end of the display panel, and electrically connecting the plurality of DDICs and the circuit board, and a thermal diffusion member disposed, between the circuit board and the display panel.

公开(公告)号：US12199044B2

公开(公告)日：2025-01-14

申请号：US17714412

申请日：2022-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghui Hong ,  Sangwon Kim ,  Jeeyong Kim ,  Subin Shin ,  Habin Lim

IPC: H10B43/27 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A peripheral circuit structure may include peripheral circuits and peripheral circuit lines on a semiconductor substrate, a semiconductor layer including cell array and connection regions on the peripheral circuit structure, a stack including electrodes stacked on the semiconductor layer having a stepwise structure on the connection region, and a planarization insulating layer covering the stack, vertical structures on the cell array region penetrating the stack, including a data storage pattern, a dam group including insulating dams on the connection region penetrating the stack, penetration plugs penetrating the insulating dams and connected to respective peripheral circuit lines, the dam group including a first insulating dam farthest from the cell array region, the first insulating dam including first and second sidewall portions spaced apart, a difference between upper and lower thicknesses of the second sidewall portion of the first insulating dam is larger than that of the first sidewall portion.

公开(公告)号：US12154490B2

公开(公告)日：2024-11-26

申请号：US18308828

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongryeol Seo ,  Sangwon Kim ,  Youngkook Kim

IPC: G09G3/30 ,  G09G3/32 ,  G09G3/36

Abstract: A display apparatus of a plurality of display apparatues constituting a wall display includes a first board, a second board, and a plurality of display modules. The first board includes a first communication interface including a circuitry for wireless transmission, and a timing controller configured to, in response to information on an image being received, generate a plurality of driving signals for driving the plurality of display modules based on the received information and transmit the plurality of driving signals to the second board through the first communication interface. The second board includes a second communication interface including circuitry for wireless reception, a plurality of interfaces electrically connected to the plurality of display modules, and an IC chip configured to, based on the plurality of driving signals being received through the second interface, provide each of the received driving signals to each of the display modules.

公开(公告)号：US12127394B2

公开(公告)日：2024-10-22

申请号：US18298230

申请日：2023-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huijung Kim ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

IPC: H10B12/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78

CPC classification number: H10B12/34 ,  H01L21/28026 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/7813 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

公开(公告)号：US20230247824A1

公开(公告)日：2023-08-03

申请号：US18298230

申请日：2023-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HUIJUNG KIM ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

IPC: H01L29/94 ,  H01L29/423 ,  H01L29/78

CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/053 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/7813

Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

公开(公告)号：US11157228B2

公开(公告)日：2021-10-26

申请号：US16835960

申请日：2020-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwon Kim ,  Jeongryeol Seo ,  Youngkook Kim

IPC: G06F3/14 ,  G09G5/12

Abstract: Disclosed is a display apparatus and a control method thereof. The display apparatus includes a display group including a master display module and a plurality of slave display modules coupled by a Daisy Chain method, a first sensor equipped on the master display module, a second sensor equipped on at least one from the plurality of slave display modules, and a processor included in the master display module. The processor is configured to, based on sensing data obtained from the second sensor being received by the master display module through the Daisy Chain method, provide the received sensing data and sensing data obtained through the first sensor to an external apparatus.