公开(公告)号：US5297096A

公开(公告)日：1994-03-22

申请号：US711547

申请日：1991-06-07

申请人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

发明人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/14 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C16/14 ,  G11C16/16

摘要： A flash EEPROM including a memory cell array divided into first and second blocks. Erase pulse applying circuits for applying erase pulses to memory cells and erase verifying circuits for erase-verifying the memory cells are provided one for each of those two blocks. The erase pulse applying circuit and the erase verifying circuit provided corresponding to the first block operate separately from the erase pulse applying circuit and the erase verifying circuit provided corresponding to the second block. The erase pulse applying circuits are each controlled by their corresponding erase verifying circuits. That is, each erase verifying circuit enables its corresponding erase pulse applying circuit only when detecting a memory cell in which a data erase is incomplete in the corresponding block.

摘要翻译： 一种快闪EEPROM，包括分为第一和第二块的存储单元阵列。 为这两个块中的每一个提供擦除用于向存储单元施加擦除脉冲的脉冲施加电路和用于擦除验证存储单元的擦除验证电路。 对应于第一块设置的擦除脉冲施加电路和擦除验证电路与擦除脉冲施加电路和对应于第二块设置的擦除验证电路分开工作。 擦除脉冲施加电路各自由其相应的擦除验证电路控制。 也就是说，每个擦除验证电路仅在检测到相应块中的数据擦除不完整的存储单元时才能使其相应的擦除脉冲施加电路。

公开(公告)号：US5132928A

公开(公告)日：1992-07-21

申请号：US501703

申请日：1990-03-30

申请人： Masanori Hayashikoshi ,  Yasushi Terada ,  Kazuo Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki

发明人： Masanori Hayashikoshi ,  Yasushi Terada ,  Kazuo Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki

IPC分类号： G11C17/00 ,  G06F11/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C29/00 ,  G11C29/42

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C16/08 ,  G11C16/26

摘要： An electrically programmable non-volatile semiconductor memory device includes a plurality of internal data transmission lines. Data communication between memory cells and the internal data transmission lines is performed for a byte of data having a plurality of bits. Each of the word lines includes a plurality of divided auxiliary word lines in association with the internal data transmission lines. Those memory cells for each word line that are to be connected to the same internal data transmission line are connected to one auxiliary word line. Only one of a plurality of memory cells connected to one auxiliary word line is connected to an internal data transmission line in operation. Therefore, a plurality of the memory cells connected to different auxiliary word lines, are connected in parallel to a plurality of the internal data transmission lines. According to this arrangement, the effect of word line destruction occasionally caused in one auxiliary word line is not extended to other auxiliary word lines, so that the damaged auxiliary word line can be repaired by the use of an error correction detection code.

摘要翻译： 电可编程非易失性半导体存储器件包括多个内部数据传输线。 对于具有多个位的数据的字节执行存储器单元与内部数据传输线之间的数据通信。 每个字线包括与内部数据传输线相关联的多个划分的辅助字线。 要连接到同一内部数据传输线的每个字线的那些存储单元连接到一个辅助字线。 连接到一个辅助字线的多个存储单元中只有一个连接到操作中的内部数据传输线。 因此，连接到不同辅助字线的多个存储单元并联连接到多个内部数据传输线。 根据这种布置，偶然地在一个辅助字线中引起的字线破坏的影响不会扩展到其他辅助字线，从而可以通过使用纠错检测码修复损坏的辅助字线。

公开(公告)号：US06515900B2

公开(公告)日：2003-02-04

申请号：US09832986

申请日：2001-04-12

申请人： Tamiyu Kato ,  Tomoshi Futatsuya ,  Yoshikazu Miyawaki

发明人： Tamiyu Kato ,  Tomoshi Futatsuya ,  Yoshikazu Miyawaki

IPC分类号： G11C1134

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/20 ,  G11C2216/22

摘要： A non-volatile semiconductor memory device includes a bank pointer, in which a signal for designating an operating mode to be performed is generated according to coincidence/non-coincidence of prescribed bits of address signals supplied from an address buffer, and the generated signal is supplied to an internal control circuit. Thus, necessary data can be read out from the non-volatile semiconductor memory device at high speed, so that usability of the device is improved.

摘要翻译： 非易失性半导体存储器件包括存储体指针，其中根据从地址缓冲器提供的地址信号的规定位的一致/非重合，生成用于指定要执行的操作模式的信号，并且所生成的信号为 提供给内部控制电路。 因此，可以高速地从非易失性半导体存储器件读出必要的数据，从而提高了器件的可用性。

公开(公告)号：US5959890A

公开(公告)日：1999-09-28

申请号：US27194

申请日：1998-02-20

申请人： Yasuhiro Yamamoto ,  Yoshikazu Miyawaki ,  Masaaki Mihara

发明人： Yasuhiro Yamamoto ,  Yoshikazu Miyawaki ,  Masaaki Mihara

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30 ,  G11C29/50

CPC分类号： G11C16/30 ,  G11C16/08 ,  G11C29/50 ,  G11C8/08 ,  G11C16/04

摘要： A non-volatile semiconductor memory device comprises a bit line 402, a plurality of word lines 401 arranged to cross the bit line 402, a plurality of non-volatile memory cells 404 which are disposed at the crossing points of the bit line 402 and the word lines 401 and which have a drain 404a connected to the bit line 402 and a control gate 404f connected to the corresponding word line 401, anda word line potential applying means 300, 500 wherein in an ordinary reading mode, a selective potential is applied to a word line 401 selected from the plurality of word lines, while a non-selective potential, which is lower than the selective potential, is applied to unselected word lines 401 in response to an address signal, and in a prescribed mode, the selective potential is applied to a word line 401 selected from the plurality of word lines, while a prescribed potential, which is lower than the non-selective potential, is applied to the unselected word lines in response to an address signal.

摘要翻译： 非易失性半导体存储器件包括位线402，布置成穿过位线402的多个字线401，多个非易失性存储器单元404，其设置在位线402和 字线401并且具有连接到位线402的漏极404a和连接到对应字线401的控制栅极404f以及字线电位施加装置300,500，其中在普通读取模式中施加选择电位 到选自多个字线的字线401，而低于选择电位的非选择性电位响应于地址信号被施加到未选字线401，并且在规定模式中，选择性地选择 电位被施加到从多个字线中选择的字线401，而低于非选择电位的规定电位响应于地址信号被施加到未选字线 l。

公开(公告)号：US5898606A

公开(公告)日：1999-04-27

申请号：US841372

申请日：1997-04-30

申请人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

发明人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

IPC分类号： G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L27/11517 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/16 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/7883

摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

摘要翻译： 在擦除时，电子同时从多个存储单元的源中注入到浮动栅极中。 因此，多个存储单元的阈值电压增加。 在编程中，电子从所选择的存储单元的浮动栅极发射到漏极。 因此，所选存储单元的阈值电压降低。

公开(公告)号：US5548557A

公开(公告)日：1996-08-20

申请号：US179731

申请日：1994-01-11

申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。

公开(公告)号：US5521863A

公开(公告)日：1996-05-28

申请号：US430032

申请日：1995-04-27

申请人： Shinichi Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Yasushi Terada

发明人： Shinichi Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Yasushi Terada

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/02

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C2216/14

摘要： A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.

摘要翻译： 消除了连接到每个位线的列锁存器和高压开关，并且新提供地址计数器和数据锁存器。 数据锁存器布置在I / O缓冲器和Y门之间。 在编程周期中，地址计数器被激活，并且连续选择Y门中的传输门。 因此，根据存储在数据锁存器中的写数据，高电压Vpp或0V周期地施加于存储单元阵列中的位线。

公开(公告)号：US5485421A

公开(公告)日：1996-01-16

申请号：US295582

申请日：1994-08-25

申请人： Shinichi Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Yasushi Terada

发明人： Shinichi Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Yasushi Terada

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/02

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C2216/14

摘要： A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.

摘要翻译： 消除了连接到每个位线的列锁存器和高压开关，并且新提供地址计数器和数据锁存器。 数据锁存器布置在I / O缓冲器和Y门之间。 在编程周期中，地址计数器被激活，并且连续选择Y门中的传输门。 因此，根据存储在数据锁存器中的写入数据，对存储单元阵列中的位线周期地施加高电压Vpp或0V。

公开(公告)号：US5283758A

公开(公告)日：1994-02-01

申请号：US794708

申请日：1991-11-20

申请人： Takeshi Nakayama ,  Yasushi Terada ,  Kazuo Kobayashi ,  Masanori Hayashikoshi ,  Yoshikazu Miyawaki

发明人： Takeshi Nakayama ,  Yasushi Terada ,  Kazuo Kobayashi ,  Masanori Hayashikoshi ,  Yoshikazu Miyawaki

IPC分类号： G11C7/18 ,  G11C16/04 ,  G11C16/16 ,  G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0425 ,  G11C16/0491 ,  G11C7/18

摘要： A plurality of memory cell transistors having floating gates are disposed in a matrix in the direction of row and column to form a memory cell array. The memory cell array is divided into a plurality of sectors for every predetermined row. In each sector, sector selecting transistors and sub bit lines are provided, so that erasing and programming can be made for each sector. Therefore, total erasing for sector becomes possible, and since no voltage is applied to sub bit lines and word lines of non-selected sectors, the number of operations of preventing writing into non-selected memory cells is as many as the word lines included in one sector.

摘要翻译： 具有浮动栅极的多个存储单元晶体管以行和列的方向设置在矩阵中以形成存储单元阵列。 存储单元阵列被划分成用于每个预定行的多个扇区。 在每个扇区中，提供扇区选择晶体管和子位线，从而可以对每个扇区进行擦除和编程。 因此，扇区的全部擦除成为可能，并且由于没有电压施加到非选择扇区的子位线和字线，所以防止写入未选择的存储单元的操作次数与包括在 一个部门。