公开(公告)号：USRE41868E1

公开(公告)日：2010-10-26

申请号：US11708145

申请日：2007-02-20

申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/08 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888 ,  H01L29/7889

摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

公开(公告)号：US07692234B2

公开(公告)日：2010-04-06

申请号：US11862928

申请日：2007-09-27

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US07528036B2

公开(公告)日：2009-05-05

申请号：US11107826

申请日：2005-04-18

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

公开(公告)号：US20080261357A1

公开(公告)日：2008-10-23

申请号：US11956858

申请日：2007-12-14

申请人： Norifumi KAMESHIRO ,  Toshiyuki Mine ,  Tomoyuki Ishii ,  Toshiaki Sano

发明人： Norifumi KAMESHIRO ,  Toshiyuki Mine ,  Tomoyuki Ishii ,  Toshiaki Sano

IPC分类号： H01L21/84

CPC分类号： H01L29/66757 ,  H01L29/66613 ,  H01L29/66772

摘要： After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.

摘要翻译： 在绝缘体层上形成源极 - 漏极材料膜之后，在源极 - 漏极材料膜中形成到达绝缘体层的开口部分。 然后，在开口部分的绝缘体层和源极 - 漏极材料膜上依次形成具有期望厚度的沟道和栅极绝缘体。 此后，在栅极绝缘体上形成嵌入开口部的栅极材料膜。 随后，在栅极材料膜上形成盖膜，从而形成由栅极材料膜制成的栅极。 然后，在源极 - 漏极材料膜上形成掩模层。 接下来，除去未被掩模层保护的源极 - 漏极材料膜，同时通过盖膜保护栅极，从而在栅极的两侧留下源极 - 漏极材料膜。 一侧的源极 - 漏极材料膜成为源极，而另一侧的源极 - 漏极材料膜变成漏极。

公开(公告)号：US20070285983A1

公开(公告)日：2007-12-13

申请号：US11790590

申请日：2007-04-26

申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

IPC分类号： G11C11/34 ,  H01L21/336

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

公开(公告)号：US20070018330A1

公开(公告)日：2007-01-25

申请号：US11526754

申请日：2006-09-26

申请人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

发明人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76813

摘要： A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4−n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.

摘要翻译： 根据本发明的半导体器件包括其中形成有半导体元件的基板100，其外围表面的至少一部分由包含铜作为主要成分的材料制成的第一导体301和第一绝缘扩散阻挡层 层203覆盖第一导体301的至少一部分。 第一绝缘扩散阻挡层203通过使用至少含有由通式（RO）表示的烷氧基硅烷的气体混合物形成（n为 1〜3的整数，R表示烷基，芳基或其衍生物）和通过等离子体CVD的氧化性气体。 因此，可以提供包括高可靠性和较少布线延迟时间的铜布线的半导体器件。

公开(公告)号：US07115943B2

公开(公告)日：2006-10-03

申请号：US11013406

申请日：2004-12-17

申请人： Toshiyuki Mine ,  Natsuki Yokoyama ,  Kan Yasui

发明人： Toshiyuki Mine ,  Natsuki Yokoyama ,  Kan Yasui

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/792

摘要： A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.

摘要翻译： 分离栅结构的MONOS非易失性存储器，其中由热电子和热孔分别执行写入和擦除容易导致电子不被擦除并且保留在选择栅极电极侧壁上的氮化硅膜中，并且结果 在改写耐久性的恶化。 当长时间擦除作为解决该问题的措施时，会出现缺点，例如由擦除电流的增加引起的电路面积的增加和保留特性的劣化。 在本发明中，通过能够进行取向沉积的反应等离子体溅射沉积方法形成氮化硅膜，并且在形成顶部Si氧化物膜时，在选择栅电极侧壁上除去Si氮化物膜。

公开(公告)号：US07042055B2

公开(公告)日：2006-05-09

申请号：US10174948

申请日：2002-06-20

申请人： Shinichi Saito ,  Kazuyoshi Torii ,  Takahiro Onai ,  Toshiyuki Mine

发明人： Shinichi Saito ,  Kazuyoshi Torii ,  Takahiro Onai ,  Toshiyuki Mine

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/62

CPC分类号： H01L29/4983 ,  H01L21/28017 ,  H01L21/28061 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： In a miniaturized field effect transistor, the roughness of the interface between a gate dielectric film and a gate electrode is controlled on an atomic scale. The thickness variation of the gate dielectric film is lowered, whereby a field effect transistor with high mobility is manufactured. An increase in the mobility in the field effect transistor can be achieved not only in the case of using a conventional SiO2 thermal oxide film as the gate dielectric film but also in the case of using a high dielectric material for the gate dielectric film.

摘要翻译： 在小型场效应晶体管中，栅介质膜与栅电极之间的界面的粗糙度被控制在原子尺度上。 栅电介质膜的厚度变化降低，由此制造具有高迁移率的场效应晶体管。 场效应晶体管的迁移率的增加不仅可以在使用常规的SiO 2热氧化膜作为栅极电介质膜的情况下实现，而且在使用高介电材料的情况下也可以实现 用于栅介质膜。

公开(公告)号：US06897104B2

公开(公告)日：2005-05-24

申请号：US10452126

申请日：2003-06-03

申请人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

发明人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film.

摘要翻译： 一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅 硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是 去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时 将氮气引入未被除去的二氧化硅的表面，依次溶解 并且移除氮导入的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面。

公开(公告)号：US20050104141A1

公开(公告)日：2005-05-19

申请号：US11000992

申请日：2004-12-02

申请人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

发明人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

摘要翻译： 提供如下配置的半导体器件。 在半导体衬底上形成作为绝缘膜的介电常数高于二氧化硅膜的氧化钛膜作为栅极绝缘膜，并且在其上设置栅电极，得到场效应晶体管。 氧化钛膜的栅极长度方向的端部位于栅电极的源极侧和漏极侧的各端部的内侧，氧化钛膜的端部位于 其中栅电极以平面构型与源区和漏区重叠。 该半导体器件以高速度工作，并且具有优异的短沟道特性和驱动电流。 此外，在半导体器件中，导入硅衬底的金属元素的量小。