公开(公告)号：US10755779B2

公开(公告)日：2020-08-25

申请号：US15701071

申请日：2017-09-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C7/06

Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.

公开(公告)号：US20200013789A1

公开(公告)日：2020-01-09

申请号：US16578104

申请日：2019-09-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

公开(公告)号：US10276236B2

公开(公告)日：2019-04-30

申请号：US15597709

申请日：2017-05-17

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology, and Research

Inventor： Santosh Hariharan ,  Hieu Van Tran ,  Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Nhan Do ,  Zhixian Chen ,  Xinpeng Wang

IPC: G11C13/00 ,  G11C11/00 ,  H01L27/24 ,  H01L45/00

Abstract: A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.

公开(公告)号：US09972630B2

公开(公告)日：2018-05-15

申请号：US15295022

申请日：2016-10-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Feng Zhou ,  Jeng-Wei Yang ,  Hieu Van Tran ,  Nhan Do

IPC: H01L21/336 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11524

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

公开(公告)号：US20180069104A1

公开(公告)日：2018-03-08

申请号：US15474879

申请日：2017-03-30

Applicant: Silicon Storage Technology Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do ,  Chunming Wang

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66825 ,  G11C2216/10 ,  H01L21/28273 ,  H01L27/0705 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/788

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US09276005B1

公开(公告)日：2016-03-01

申请号：US14560475

申请日：2014-12-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell includes source and drain regions in a substrate with a channel region therebetween, an erase gate over the source region, a floating gate over a first channel region portion, a control gate over the floating gate, and a wordline gate over a second channel region portion. A first logic device includes second source and drain regions in the substrate with a second channel region therebetween under a first logic gate. A second logic device includes third source and drain regions in the substrate with a third channel region therebetween under a second logic gate. The wordline gate and the first and second logic gates comprise the same conductive metal material. The second logic gate is insulated from the third channel region by first and second insulation. The first logic gate is insulated from the second channel region by the second insulation and not by the first insulation.

Abstract translation: 存储单元包括在其中具有沟道区域的衬底中的源极和漏极区域，源极区域上的擦除栅极，在第一沟道区域部分上的浮动栅极，浮置栅极上的控制栅极以及第二沟道区域上的字线栅极 通道区域部分。 第一逻辑器件包括衬底中的第二源极和漏极区域，在第一逻辑门之下具有第二沟道区域。 第二逻辑器件包括衬底中的第三源极和漏极区域，在第二逻辑门极之间具有第三沟道区域。 字线栅极和第一和第二逻辑门包括相同的导电金属材料。 第二逻辑门通过第一和第二绝缘与第三沟道区绝缘。 第一逻辑门通过第二绝缘而与第二沟道区绝缘，而不是通过第一绝缘。

公开(公告)号：US20230238453A1

公开(公告)日：2023-07-27

申请号：US18126954

申请日：2023-03-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  XIAN LIU ,  CHIEN-SHENG SU ,  Nhan DO ,  CHUNMING WANG

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/07 ,  H01L29/08 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L29/788 ,  H01L27/0705 ,  H01L29/0847 ,  H01L29/40114 ,  H01L28/00 ,  H01L29/42328 ,  H01L29/66545 ,  G11C2216/10 ,  H01L29/6653

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US11652162B2

公开(公告)日：2023-05-16

申请号：US17021678

申请日：2020-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do ,  Chunming Wang

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/07 ,  H01L29/08 ,  H01L21/28 ,  H01L49/02 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L27/0705 ,  H01L28/00 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/788 ,  G11C2216/10 ,  H01L29/6653

Abstract: A simplified method for forming a non-volatile memory cell using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. An insulation block is formed on the first polysilicon layer. Spacers are formed adjacent first and second sides of the insulation block, and with the spacer adjacent the first side is reduced. Exposed portions of the first poly silicon layer are removed while maintaining a polysilicon block of the first polysilicon layer disposed under the insulation block. A second polysilicon layer is formed over the substrate and the insulation block in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed adjacent the first side of the insulation block), and a second polysilicon block (disposed adjacent the second side of the insulation block).

公开(公告)号：US20200176459A1

公开(公告)日：2020-06-04

申请号：US16208150

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  JINHO KIM ,  XIAN LIU ,  SERGUEI JOURBA ,  CATHERINE DECOBERT ,  NHAN DO

IPC: H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.

公开(公告)号：US20200013788A1

公开(公告)日：2020-01-09

申请号：US16422740

申请日：2019-05-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/11524 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/088 ,  H01L21/266 ,  H01L29/788 ,  H01L29/78 ,  H01L29/423

Abstract: A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first fin, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.