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公开(公告)号：US07910904B2
公开(公告)日：2011-03-22
申请号：US11127482
申请日：2005-05-12
申请人： Charles C. Kuo , Ilya V. Karpov
发明人： Charles C. Kuo , Ilya V. Karpov
IPC分类号： H01L29/02
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/1683 , Y10S438/90
摘要： A phase change memory may be formed which is amenable to multilevel programming. The phase change material may be formed with a lateral extent which does not exceed the lateral extent of an underlying heater. As a result, the possibility of current bypassing the amorphous phase change material in the reset state is reduced, reducing the programming current that is necessary to prevent this situation. In addition, a more controllable multilevel phase change memory may be formed in some embodiments.
摘要翻译： 可以形成适于多级编程的相变存储器。 相变材料可以形成有不超过下面的加热器的横向范围的横向范围。 结果，减少了在复位状态下绕过非晶相变材料的电流的可能性，从而减少了防止这种情况所必需的编程电流。 此外，在一些实施例中可以形成更可控的多电平相变存储器。
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公开(公告)号：US07863596B2
公开(公告)日：2011-01-04
申请号：US11531800
申请日：2006-09-14
申请人： Ilya V. Karpov , Sergey Kostylev , Charles C. Kuo
发明人： Ilya V. Karpov , Sergey Kostylev , Charles C. Kuo
IPC分类号： H01L47/00
CPC分类号： H01L45/141 , G11C11/5678 , G11C13/0004 , G11C2013/008 , H01L27/2427 , H01L45/06 , H01L45/122 , H01L45/126 , H01L45/144 , H01L45/1691
摘要： A ring shaped heater surrounds a chalcogenide region along the length of a cylindrical solid phase portion thereof defining a change phase memory element. The chalcogenide region is formed in a sub-lithographic pore, so that a relatively compact structure is achieved. Furthermore, the ring contact between the heater and the cylindrical solid phase portion results in a more gradual transition of resistance versus programming current, enabling multilevel memories to be formed.
摘要翻译： 环形加热器沿着限定变化相位存储元件的圆柱形固相部分的长度围绕硫族化物区域。 硫族化物区形成在亚光刻孔中，从而实现了相对紧凑的结构。 此外，加热器和圆柱形固相部分之间的环接触导致电阻相对于编程电流的更渐进的转变，使得能够形成多层存储器。
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公开(公告)号：US07455571B1
公开(公告)日：2008-11-25
申请号：US11765649
申请日：2007-06-20
CPC分类号： B24B37/205
摘要： A window polishing pad having a reduced stress pad window formed therein for performing optical end point detection are provided, wherein the window polishing pad comprises a pad window and a pressure relief channel, wherein the pressure relief channel extends to an outer periphery of the window polishing pad from a cavity formed behind the pad window when the window polishing pad is interfaced with a platen and wherein a membrane is provided over at least one of an inlet and an outlet of the pressure relief channel. Also disclosed are methods of making and of using the window polishing pads to polish a semiconductor wafer.
摘要翻译： 提供了一种在其中形成的用于进行光学终点检测的具有减小的应力垫窗口的窗口抛光垫，其中所述窗户抛光垫包括垫窗口和压力释放通道，其中所述压力释放通道延伸到所述窗户抛光的外周边 当窗玻璃抛光垫与压板接合时，形成在垫窗口后面的空腔中，并且其中在压力释放通道的入口和出口中的至少一个上提供膜。 还公开了制造和使用窗口抛光垫以抛光半导体晶片的方法。
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34.发明申请Programming a normally single phase chalcogenide material for use as a memory of FPLA 有权编程正常的单相硫族化物材料，用作FPLA的记忆公开(公告)号：US20080273379A1
公开(公告)日：2008-11-06
申请号：US12218122
申请日：2008-07-11
申请人： George A. Gordon , Ward D. Parkinson , John M. Peters , Tyler A. Lowrey , Stanford Ovshinsky , Guy C. Wicker , Ilya V. Karpov , Charles C. Kuo
发明人： George A. Gordon , Ward D. Parkinson , John M. Peters , Tyler A. Lowrey , Stanford Ovshinsky , Guy C. Wicker , Ilya V. Karpov , Charles C. Kuo
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2013/0092 , G11C2213/77 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.
摘要翻译： 可以用稳定的硫属化物玻璃来实现记忆，硫化物玻璃被定义为当暴露于200℃下30分钟或更短时不改变为通常结晶相的通常为非晶态的硫族化物材料。 可以通过改变材料的阈值电压来编程不同的状态。 可以用不同幅度和/或不同脉冲下降时间的脉冲来改变阈值电压。 可以使用两种不同状态的阈值电压之间的参考电平进行读取。 通常不需要单独的访问设备。
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35.发明申请公开(公告)号：US20180350418A1
公开(公告)日：2018-12-06
申请号：US15779029
申请日：2015-12-24
申请人： Brian S. Doyle , Elijah V. Karpov , Kaan Oguz , Kevin P. O'Brien , Charles C. Kuo , Mark L. Doczy , Uday Shah , Yih Wang
发明人： Brian S. Doyle , Elijah V. Karpov , Kaan Oguz , Kevin P. O'Brien , Charles C. Kuo , Mark L. Doczy , Uday Shah , Yih Wang
CPC分类号： G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5607 , G11C2211/5615 , H01L27/228 , H01L43/08
摘要： Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.
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公开(公告)号：US09647208B2
公开(公告)日：2017-05-09
申请号：US14950784
申请日：2015-11-24
申请人： Elijah V. Karpov , Brian S. Doyle , Charles C. Kuo , Robert S. Chau , Eric R. Dickey , Michael Stephen Bowen , Sey-Shing Sun
发明人： Elijah V. Karpov , Brian S. Doyle , Charles C. Kuo , Robert S. Chau , Eric R. Dickey , Michael Stephen Bowen , Sey-Shing Sun
CPC分类号： H01L45/08 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147
摘要： Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.
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37.发明申请LOW VOLTAGE EMBEDDED MEMORY HAVING CONDUCTIVE OXIDE AND ELECTRODE STACKS 审中-公开具有导电氧化物和电极堆叠的低电压嵌入式存储器公开(公告)号：US20160079523A1
公开(公告)日：2016-03-17
申请号：US14950784
申请日：2015-11-24
申请人： Elijah V. Karpov , Brian S. Doyle , Charles C. Kuo , Robert S. Chau , Eric R. Dickey , Michael Stephen Bowen , Sey-Shing Sun
发明人： Elijah V. Karpov , Brian S. Doyle , Charles C. Kuo , Robert S. Chau , Eric R. Dickey , Michael Stephen Bowen , Sey-Shing Sun
CPC分类号： H01L45/08 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147
摘要： Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.
摘要翻译： 描述具有导电氧化物和电极堆叠的低电压嵌入式存储器。 例如，用于存储元件的材料层堆叠包括第一导电电极。 导电氧化物层设置在第一导电电极上。 导电氧化物层中具有多个氧空位。 第二电极设置在导电氧化物层上。
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38.发明授权Techniques and configuration for stacking transistors of an integrated circuit device 有权用于堆叠集成电路器件的晶体管的技术和配置公开(公告)号：US09236476B2
公开(公告)日：2016-01-12
申请号：US13997972
申请日：2011-12-28
申请人： Ravi Pillarisetty , Charles C. Kuo , Han Wui Then , Gilbert Dewey , Willy Rachmady , Van H. Le , Marko Radosavljevic , Jack T. Kavalieros , Niloy Mukherjee
发明人： Ravi Pillarisetty , Charles C. Kuo , Han Wui Then , Gilbert Dewey , Willy Rachmady , Van H. Le , Marko Radosavljevic , Jack T. Kavalieros , Niloy Mukherjee
IPC分类号： H01L29/78 , H01L29/786 , H01L21/84 , H01L29/423 , H01L27/12 , G11C11/412 , H01L29/66 , H01L27/06
CPC分类号： H01L29/785 , G11C11/412 , H01L21/845 , H01L27/0688 , H01L27/1211 , H01L29/4232 , H01L29/42392 , H01L29/66795 , H01L29/78696
摘要： Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例提供了用于堆叠存储器件的晶体管的技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的多个翅片结构，其中，多个翅片结构的单个翅片结构包括设置在半导体衬底上的第一隔离层， 第一隔离层，设置在第一沟道层上的第二隔离层和设置在第二隔离层上的第二沟道层，以及与第一沟道层电容耦合以控制通过第一沟道层的电流的栅极端子 用于第一晶体管，并与第二沟道层电容耦合，以控制通过第二沟道层的电流流向第二晶体管。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09166150B2
公开(公告)日：2015-10-20
申请号：US13725235
申请日：2012-12-21
CPC分类号： H01L43/02 , G11C11/155 , G11C11/161 , G11C11/1675 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
摘要： Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.
摘要翻译： 具有用于施加电场的场板的旋转转矩存储器（STTM）装置，以减少传递转矩感应磁化切换所需的临界电流。 实施例不仅利用电流感应磁场或自旋转移转矩，还利用电场诱导的磁偶极取向的操纵来设置磁性器件元件中的状态（例如，写入存储元件）。 由MTJ电极和场板之间的电压差产生的电场向磁性隧道结（MTJ）的自由磁性层施加电场，以在至少一部分自由磁性层上调制一个或多个磁性能 。
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公开(公告)号：US20140299953A1
公开(公告)日：2014-10-09
申请号：US14312125
申请日：2014-06-23
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1659 , H01L43/02 , H01L43/08
摘要： The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
摘要翻译： 本公开涉及用于非易失性微电子存储器件的自旋转移转矩存储元件的制造。 自旋转移转矩存储元件可以包括与特定尺寸和/或形状的固定磁性层连接的磁性隧道结，其可以定位在与自由磁性层相邻的特定位置。 成形的固定磁性层可以将电流集中在自由磁性层中，这可能导致在自旋转移转矩存储元件中切换位单元所需的临界电流的降低。
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