公开(公告)号：US20190131382A1

公开(公告)日：2019-05-02

申请号：US15795610

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chien-Hsing Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L49/02 ,  H01L21/02

Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

公开(公告)号：US09698060B2

公开(公告)日：2017-07-04

申请号：US15005424

申请日：2016-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8256 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/08

CPC classification number: H01L21/8256 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/7848

Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.

公开(公告)号：US20160155668A1

公开(公告)日：2016-06-02

申请号：US15005424

申请日：2016-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

IPC: H01L21/8256 ,  H01L29/08 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/8256 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/7848

Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.

Abstract translation: 集成电路结构包括n型鳍式场效应晶体管（FinFET）和p型FinFET。 n型FinFET包括在衬底上的第一锗鳍; 顶表面上的第一栅电介质和第一锗鳍的侧壁; 以及在第一栅极电介质上的第一栅电极。 p型FinFET在衬底上包括第二个锗鳍; 在顶表面上的第二栅电介质和第二锗鳍的侧壁; 和在第二栅极电介质上的第二栅电极。 第一栅电极和第二栅极由具有接近锗的固有能级的功函数的相同材料形成。

公开(公告)号：US12256552B2

公开(公告)日：2025-03-18

申请号：US18525301

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Sheng Chang

IPC: H10B51/30 ,  G11C11/22 ,  H01L49/02

Abstract: A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.

公开(公告)号：US20240114691A1

公开(公告)日：2024-04-04

申请号：US18525301

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Sheng Chang

IPC: H10B51/30 ,  G11C11/22

CPC classification number: H10B51/30 ,  G11C11/223 ,  G11C11/2275 ,  G11C11/2297 ,  H01L28/75

Abstract: A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.

公开(公告)号：US11942380B2

公开(公告)日：2024-03-26

申请号：US17080625

申请日：2020-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Shiang Lin ,  Chia-Cheng Ho ,  Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chih-Sheng Chang

IPC: H01L29/417 ,  G01R27/26 ,  H01L21/283 ,  H01L21/306 ,  H01L21/324 ,  H01L21/66 ,  H01L29/66

CPC classification number: H01L22/14 ,  G01R27/2617 ,  H01L22/34

Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

公开(公告)号：US11764267B2

公开(公告)日：2023-09-19

申请号：US17086017

申请日：2020-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Meng-Hsuan Hsiao ,  Tung-Ying Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L21/465 ,  H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H10B12/00 ,  H10B51/00 ,  H10B51/40 ,  H10B63/00 ,  H01L29/10 ,  H01L23/31 ,  H01L29/51 ,  H01L29/08 ,  H01L21/768 ,  H01L29/06 ,  H01L21/441 ,  H01L27/092 ,  H01L29/778 ,  H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L21/3105 ,  H01L21/027

CPC classification number: H01L29/1033 ,  H01L21/441 ,  H01L21/465 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/3171 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0642 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/516 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78391 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/78696 ,  H10B12/056 ,  H10B12/36 ,  H10B51/00 ,  H10B51/40 ,  H10B63/34 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/0273 ,  H01L21/02112 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02521 ,  H01L21/02568 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/24

Abstract: A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer.

公开(公告)号：US11631755B2

公开(公告)日：2023-04-18

申请号：US17179954

申请日：2021-02-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chien-Hsing Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/94 ,  H01L29/51 ,  H01L29/78

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

公开(公告)号：US11114540B2

公开(公告)日：2021-09-07

申请号：US16585515

申请日：2019-11-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Hsing Lee ,  Chih-Sheng Chang ,  Wilman Tsai ,  Chia-Wen Chang ,  Ling-Yen Yeh ,  Carlos H. Diaz

IPC: H01L29/51 ,  H01L27/11 ,  H01L27/092 ,  H01L21/28 ,  H01L29/16 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.

公开(公告)号：US11037835B2

公开(公告)日：2021-06-15

申请号：US16392189

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Tzu-Chiang Chen ,  Chih-Sheng Chang ,  Cheng-Hsien Wu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/04 ,  H01L29/775 ,  H01L27/092 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.