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    Gate all-around semiconductor device and manufacturing method thereof
    31.
    发明授权
    Gate all-around semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10170378B2

    公开(公告)日：2019-01-01

    申请号：US15498748

    申请日：2017-04-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Gerben Doornbos ,  Chung-Te Lin ,  Mark Van Dal

    IPC: H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: Semiconductor device includes first and second nanowire structures disposed on semiconductor substrate extending in first direction on substrate. First nanowire structure includes plurality of first nanowires including first nanowire material extending along first direction and arranged in second direction, second direction substantially perpendicular to first direction. Second nanowire structure includes plurality of second nanowires including second nanowire material extending along first direction arranged in second direction. Second nanowire material is not same as first nanowire material. Each nanowire is spaced-apart from immediately adjacent nanowire. First and second gate structures wrap around first and second nanowires at first region of respective first and second nanowire structures. First and second gate structures include gate electrodes. Viewed in cross section taken along third direction substantially perpendicular to first and second directions, height of first nanowires along second direction is not equal to distance of spacing along second direction between immediately adjacent second nanowires.

    Semiconductor Device with Air-Spacer
    32.
    发明申请
    Semiconductor Device with Air-Spacer 审中-公开

    公开(公告)号：US20180166553A1

    公开(公告)日：2018-06-14

    申请号：US15623539

    申请日：2017-06-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Chung-Te Lin ,  Yen-Ming Chen

    IPC: H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/302

    Abstract: A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.

    Three-dimensional memory device and method
    39.
    发明授权
    Three-dimensional memory device and method 有权

    公开(公告)号：US12027412B2

    公开(公告)日：2024-07-02

    申请号：US17814626

    申请日：2022-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

    IPC: H01L21/762 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

    CPC classification number: H01L21/76237 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

    Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

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