公开(公告)号：US08234441B2

公开(公告)日：2012-07-31

申请号：US13008189

申请日：2011-01-18

申请人： Kunio Uchiyama ,  Osamu Nishii

发明人： Kunio Uchiyama ,  Osamu Nishii

IPC分类号： G06F12/00

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

摘要： A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.

摘要翻译： 一种处理器系统，包括：具有处理器核心和控制器核心的处理器; 以及多个同步存储器芯片，其中所述处理器和所述多个同步存储器芯片经由外部总线连接; 其中所述处理器核心和所述控制器核心经由内部总线连接; 其中所述多个同步存储器芯片根据时钟信号被操作; 其中所述控制器核心包括通过来自所述处理器核心的地址信号选择的模式寄存器，并且通过来自所述处理器核心的数据信号写入信息以选择所述多个同步存储器芯片的操作模式;以及控制单元， 基于写在模式寄存器中的信息，向多个同步存储器芯片操作模式，其中控制器核心基于写入模式寄存器中的信息或从处理器核心到多个存储器芯片的访问地址信号输出模式设置信号 选择性地通过外部总线的同步存储器芯片; 并且其中所述时钟信号被共同地提供给所述多个同步存储器芯片。

公开(公告)号：US07958379B2

公开(公告)日：2011-06-07

申请号：US12346268

申请日：2008-12-30

申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  B23K11/24

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US07376783B2

公开(公告)日：2008-05-20

申请号：US11598661

申请日：2006-11-14

申请人： Kunio Uchiyama ,  Osamu Nishii

发明人： Kunio Uchiyama ,  Osamu Nishii

IPC分类号： G06F12/00

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

摘要： A chip including: a microprocessor; a control unit coupled to the microprocessor; and interface nodes for coupling a synchronous dynamic memory; wherein the control unit generates command information and the interface nodes output the command information to the synchronous dynamic memory in synchronism with a clock signal, wherein the command information includes a mode register set function which sets mode information to a mode register in the synchronous dynamic memory, and wherein the control unit outputs the mode information to address signal input terminals of the synchronous dynamic memory.

摘要翻译： 芯片包括：微处理器; 耦合到所述微处理器的控制单元; 以及用于耦合同步动态存储器的接口节点; 其中所述控制单元产生命令信息，并且所述接口节点与时钟信号同步地将所述命令信息输出到所述同步动态存储器，其中所述命令信息包括将模式信息设置到所述同步动态存储器中的模式寄存器的模式寄存器设置功能 并且其中所述控制单元将所述模式信息输出到所述同步动态存储器的地址信号输入端子。

公开(公告)号：US20060146635A1

公开(公告)日：2006-07-06

申请号：US11363060

申请日：2006-02-28

申请人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

发明人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

IPC分类号： G11C5/14

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/147 ,  G11C11/417 ,  Y02D10/171

摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

公开(公告)号：US06879188B2

公开(公告)日：2005-04-12

申请号：US10322594

申请日：2002-12-19

申请人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

发明人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F1/32 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03L7/07 ,  H03L7/081 ,  H03L7/099 ,  H03B19/00

CPC分类号： H03L7/07 ,  G06F1/04 ,  G06F1/3203 ,  H03L7/0812 ,  H03L7/0995 ,  Y02D10/126

摘要： A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.

摘要翻译： 一种采用两个时钟信号发生电路的半导体集成电路器件，其输出时钟信号以分配到器件的内部电路，具有不同时钟稳定时间的第一和第二时钟信号发生电路及其选择是从器件外部实现的 。 时钟信号发生电路中的第一个使用例如具有大的时钟稳定时间的锁相环电路，并且第二时钟信号发生电路例如使用延迟锁定环电路来实现， 时钟建立时间很小，例如2-3个周期。 由于具有小的时钟建立时间的第二时钟信号产生电路的选择性致动，当器件的内部电路停止时也可以停止内部电路的时钟信号的产生，从而进一步降低功耗 而不会影响时钟振荡器的响应。

公开(公告)号：US06515519B1

公开(公告)日：2003-02-04

申请号：US09580646

申请日：2000-05-30

申请人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

发明人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

IPC分类号： H03B1900

CPC分类号： H03L7/07 ,  G06F1/04 ,  G06F1/3203 ,  H03L7/0812 ,  H03L7/0995 ,  Y02D10/126

摘要： A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.

摘要翻译： 来自晶体谐振器或外部时钟信号的信号从端子xta1或exta1输入，并且来自晶体谐振器或外部时钟信号的信号由模式端子mod8选择并输入到振荡器OSC。 输入时钟信号ck11由分频器DIV1分频为期望值。 输入分频时钟信号clk2作为锁相环路PLL1或延迟锁定环路DLL1的基准时钟，由选择器SEL3选择的电路输出的时钟信号通过分配器DIV2通过分配给LSI。 锁相环PLL1具有至少40个时钟周期的时钟建立时间，而延迟锁定环DLL1的时钟建立时间为2-3个周期。

公开(公告)号：US06260107B1

公开(公告)日：2001-07-10

申请号：US09520726

申请日：2000-03-08

申请人： Kunio Uchiyama ,  Osamu Nishii

发明人： Kunio Uchiyama ,  Osamu Nishii

IPC分类号： G06F1202

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

摘要： A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

摘要翻译： 主存储装置是具有多个存储体的同步动态存储器和用于确定操作模式的模式寄存器，主存储控制器耦合到处理器和主存储装置，以及用于实现对并行访问的控制的装置 在主存储控制器中布置有多个存储器组以及将操作模式设置到内置寄存器的控制。 因此，可以确保使用高通用性和常规存储器的常规处理器。

公开(公告)号：US6154807A

公开(公告)日：2000-11-28

申请号：US188902

申请日：1998-11-10

申请人： Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

发明人： Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0215 ,  G06F13/1631

摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

摘要翻译： 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。

公开(公告)号：US6078983A

公开(公告)日：2000-06-20

申请号：US862322

申请日：1997-05-23

申请人： Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

发明人： Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

IPC分类号： G06F15/16 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/36

CPC分类号： G06F13/1642 ,  G06F13/1605

摘要： A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, first and second arbiters, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. When a processor requires data from the memory bank, the processor sends a processor ID with a data access request. When the memory bank sends data in return, the memory bank outputs the processor ID of the request originator with the required data. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access requested need not wait for a previous access request to be finished. According, the throughput of the system can be improved greatly. The first and second arbiters serve to decide ownership of buses.

摘要翻译： 本发明的多处理器系统具有地址总线，数据总线，第一和第二处理器，四个访问队列，第一和第二仲裁器以及被划分成四个存储体的共享存储器。 四个访问队列由用于缓冲通过地址总线发送的多个访问请求地址的先进先出存储器构成。 当处理器需要来自存储体的数据时，处理器发送具有数据访问请求的处理器ID。 当存储体返回数据时，存储体输出请求发起者的处理器ID和所需的数据。 即使连续访问请求被寻址到共享存储器的一个组，请求的后续访问也不需要等待先前的访问请求完成。 据说，系统的吞吐量可以大大提高。 第一和第二仲裁者用于决定公共汽车的所有权。

公开(公告)号：US5301285A

公开(公告)日：1994-04-05

申请号：US940762

申请日：1992-09-04

申请人： Makoto Hanawa ,  Osamu Nishii ,  Susumu Narita ,  Kunio Uchiyama

发明人： Makoto Hanawa ,  Osamu Nishii ,  Susumu Narita ,  Kunio Uchiyama

IPC分类号： G06F9/34 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3822

摘要： A data processor is provided with a first register storing a first half word of one instruction; a second register storing a second half word of the instruction; a first decoder decoding the first half word and at the same time detecting whether there exists an addressing extension portion between the first half word and the second half word; a second decoder decoding the second half word; and, a decode result generating circuit, to which a detection signal of the first decoder indicates whether the addressing extension portion exists. A decode result of the first decoder and a decode result of the second decoder are supplied to the decode result generating circuit. An extension portion register is provided to store the addressing extension portion. When the first decoder detects the addressing extension portion, the decode result generating circuit invalidates the decode result of the second decoder. On the other hand, in the case where there exists no addressing extension portion, the decode result generating circuit judges, on the basis of the detection signal, that the decode result of the second decoder is valid.

摘要翻译： 数据处理器设置有存储一个指令的前半字的第一寄存器; 存储指令的第二个半字的第二寄存器; 解码所述前半字，并且同时检测在所述前半字和所述第二半字之间是否存在寻址扩展部分的第一解码器; 解码所述第二半字的第二解码器; 以及第一解码器的检测信号指示寻址扩展部分是否存在的解码结果生成电路。 第一解码器的解码结果和第二解码器的解码结果被提供给解码结果生成电路。 提供扩展部分寄存器以存储寻址扩展部分。 当第一解码器检测到寻址扩展部分时，解码结果生成电路使第二解码器的解码结果无效。 另一方面，在不存在寻址扩展部的情况下，解码结果生成电路根据检测信号判断第二解码器的解码结果有效。