公开(公告)号：US09031234B2

公开(公告)日：2015-05-12

申请号：US13050165

申请日：2011-03-17

申请人： Takeshi Kawabata ,  Hideo Shimizu

发明人： Takeshi Kawabata ,  Hideo Shimizu

IPC分类号： H04L9/00 ,  H04L9/06

CPC分类号： H04L9/0631 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/24

摘要： According to one embodiment, an encryption device includes a storage unit, an input unit, first to fourth partial encryption units, a generation unit, and an output unit. The first partial encryption unit calculates first intermediate data from input plain data to store in the storage unit. The generation unit generates a round key, which is used in calculations for the first intermediate data and N-th intermediate data, from the secret key. The second partial encryption unit calculates (i+1)th intermediate data from i-th intermediate data (i is smaller than N) and the round key to store in the storage unit. The third partial encryption unit performs an arithmetic operation including predetermined conversion for mixing the N-th intermediate data, and calculates (N+1)th intermediate data to store in the storage unit. The fourth partial encryption unit obtains encrypted data by performing an arithmetic operation including inverse conversion of the conversion on the (N+1)th intermediate data.

摘要翻译： 根据一个实施例，加密装置包括存储单元，输入单元，第一至第四部分加密单元，生成单元和输出单元。 第一部分加密单元从输入的普通数据计算第一中间数据以存储在存储单元中。 生成单元从秘密密钥生成用于计算第一中间数据和第N中间数据的循环密钥。 第二部分加密单元计算第i个中间数据（i小于N）的第（i + 1）个中间数据和存储在存储单元中的循环密钥。 第三部分加密单元执行包括用于混合第N个中间数据的预定转换的算术运算，并且计算（N + 1）个中间数据以存储在存储单元中。 第四部分加密单元通过执行包括对第（N + 1）个中间数据的转换的逆转换的算术运算来获得加密数据。

公开(公告)号：US20110156271A1

公开(公告)日：2011-06-30

申请号：US12976307

申请日：2010-12-22

申请人： Takeshi Kawabata

发明人： Takeshi Kawabata

IPC分类号： H01L23/48

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor module having a second semiconductor package 200 mounted on a first semiconductor package 100, wherein the first semiconductor package 100 includes: pads 15 formed on the top surface of the first semiconductor package 100; external connection terminals 2 formed on the underside of the first semiconductor package 100, and vias 18 electrically connecting the pads 15 and the connection terminals 2. In a radiographic plane viewed in a vertical direction relative to one surface of a second substrate 25 of the second semiconductor package 200, the via 18 overlaps one of the pad 15 and the connection terminal 2, the pad 15 and the connection terminal 2 overlap each other, and the pad 15 has the center position outside the connection terminal 2.

摘要翻译： 一种具有安装在第一半导体封装100上的第二半导体封装200的半导体模块，其中第一半导体封装100包括：形成在第一半导体封装100的顶表面上的焊盘15; 形成在第一半导体封装100的下侧上的外部连接端子2以及电连接焊盘15和连接端子2的通孔18.在垂直方向上相对于第二半导体封装100的第二基板25的一个表面观察的放射照相平面 半导体封装200，通孔18与焊盘15和连接端子2中的一个重叠，焊盘15和连接端子2彼此重叠，并且焊盘15具有位于连接端子2外部的中心位置。

公开(公告)号：US20110107336A1

公开(公告)日：2011-05-05

申请号：US12926251

申请日：2010-11-04

申请人： Hiroyoshi Haruki ,  Mikio Hashimoto ,  Takeshi Kawabata

发明人： Hiroyoshi Haruki ,  Mikio Hashimoto ,  Takeshi Kawabata

IPC分类号： G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/30123 ,  G06F9/485

摘要： A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.

摘要翻译： 微处理器执行流水线架构中的程序，其包括任务寄存器管理单元，该任务寄存器管理单元将任务寄存器的值切换到在完成第一任务的执行之后执行第二任务时所使用的第二寄存器信息，如果切换指令 当多个单元执行第一任务时发出第二任务;以及任务管理器，其在将值切换到第二登记信息之后将任务识别信息寄存器的值切换到第二任务标识符，并且授予每个 多个单元允许执行第二任务。

公开(公告)号：US20100295186A1

公开(公告)日：2010-11-25

申请号：US12783836

申请日：2010-05-20

申请人： Takeshi Kawabata ,  Takashi YUI

发明人： Takeshi Kawabata ,  Takashi YUI

IPC分类号： H01L25/065 ,  H01L23/488 ,  H01L23/538

CPC分类号： H01L23/49838 ,  H01L23/49811 ,  H01L23/49827 ,  H01L25/105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00 ,  H01L2924/00014

摘要： A pad (15) is provided on a surface connecting a first substrate (11) of a lower layer module with an upper layer module, the pad is partially covered by an insulating film (20) to form an opening section (3) exposing the pad (15), a first connection terminal (2) is formed on the lower surface of the first substrate (11) of the lower layer module, the planar shape of the opening section (3) is different from the planar shape of the first connection terminal (2), the outer shape of the opening section (3) is larger than the first connection terminal (2), and in a transmissive inspection from above, the shape of the lower end of a second connection terminal (30) spreading in the opening section (3) is not concealed by the other terminal. This configuration enables easy and reliable determination of whether bonding sections are satisfactory by a non-destructive inspection.

摘要翻译： 在连接下层模块的第一基板（11）与上层模块的表面上设置焊盘（15），所述焊盘部分被绝缘膜（20）覆盖以形成露出 衬垫（15），在下层模块的第一衬底（11）的下表面上形成第一连接端子（2），开口部分（3）的平面形状不同于第一衬底 连接端子（2），开口部（3）的外形大于第一连接端子（2），在从上方透射检查中，第二连接端子（30）的下端的形状扩展 在开口部（3）中没有被另一个端子隐藏。 该结构能够通过非破坏性检查来容易且可靠地确定接合部分是否令人满意。

公开(公告)号：US07498668B2

公开(公告)日：2009-03-03

申请号：US11475174

申请日：2006-06-27

申请人： Takeshi Kawabata ,  Fumito Itou

发明人： Takeshi Kawabata ,  Fumito Itou

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A lower module of a stacked semiconductor device includes a first substrate and a first semiconductor chip held above the first substrate. The top surface of the first substrate is provided with a plurality of first chip connection terminals electrically connected to the first chip terminals, respectively, and a plurality of upper module connection terminals electrically connectable to an upper module provided with a second semiconductor chip. The back surface of the first substrate is provided with a plurality of external substrate connection terminals. Each of the first chip connection terminals is electrically connected to a corresponding one of the external substrate connection terminals, and each of the upper module connection terminals is electrically connected between a corresponding one of the chip connection terminals and a corresponding one of the external substrate connection terminals.

摘要翻译： 叠层半导体器件的下模块包括第一衬底和保持在第一衬底上的第一半导体芯片。 第一基板的顶表面分别设置有电连接到第一芯片端子的多个第一芯片连接端子和多个上模块连接端子，电连接到具有第二半导体芯片的上模块。 第一基板的背面设置有多个外部基板连接端子。 每个第一芯片连接端子电连接到对应的一个外部基板连接端子，并且每个上部模块连接端子电连接在相应的一个芯片连接端子与相应的一个外部基板连接 终端。

公开(公告)号：US07365416B2

公开(公告)日：2008-04-29

申请号：US11242904

申请日：2005-10-05

申请人： Takeshi Kawabata ,  Motoaki Satou ,  Toshiyuki Fukuda ,  Toshio Tsuda ,  Kazuhiro Nobori ,  Seiichi Nakatani

发明人： Takeshi Kawabata ,  Motoaki Satou ,  Toshiyuki Fukuda ,  Toshio Tsuda ,  Kazuhiro Nobori ,  Seiichi Nakatani

IPC分类号： H01L23/02

CPC分类号： H01L23/49816 ,  H01L21/486 ,  H01L21/563 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1627 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor module is formed by alternately stacking resin boards 3 on which semiconductor chips 2 are mounted and sheet members having openings larger than the semiconductor chips 2 and bonded to the resin boards 3. The resin board 4 located at the bottom out of the resin boards 3 is thicker than the other resin boards 3.

摘要翻译： 半导体模块通过交替堆叠安装有半导体芯片2的树脂板3和具有比半导体芯片2大的开口的片状部件并且结合到树脂板3而形成。 位于树脂基板3的底部的树脂基板4比其他树脂基板3厚。

公开(公告)号：US20060005260A1

公开(公告)日：2006-01-05

申请号：US11159230

申请日：2005-06-23

申请人： Hiroyoshi Haruki ,  Mikio Hashimoto ,  Takeshi Kawabata

发明人： Hiroyoshi Haruki ,  Mikio Hashimoto ,  Takeshi Kawabata

IPC分类号： G06F17/30 ,  G06F7/04 ,  G06K9/00 ,  H03M1/68 ,  H04K1/00 ,  H04L9/00 ,  H04L9/32 ,  H04N7/16

CPC分类号： G06F21/57

摘要： A microprocessor includes a decryption unit that decrypts information to be utilized by a processor core to obtain plaintext information when the acquired information is encrypted; and a plaintext information storing unit that stores the plaintext information. The microprocessor also includes a protected attribute adding unit that adds a protected attribute indicating one of protection and non-protection to the plaintext information based on whether the decryption has been performed; an access request acquiring unit that acquires an access request to the plaintext information; a request type identifying unit that identifies a type of request of the access request; and an access controlling unit that controls an access to the plaintext information based on the type of request and the protected attribute.

摘要翻译： 微处理器包括一个解密单元，当所获取的信息被加密时，解密由处理器核心利用的信息以获取明文信息; 以及存储明文信息的明文信息存储单元。 微处理器还包括受保护属性添加单元，该保护属性添加单元基于是否执行了解密，向明文信息添加指示保护和非保护之一的受保护属性; 访问请求获取单元，其获取对所述明文信息的访问请求; 识别访问请求的请求的类型的请求类型识别单元; 以及访问控制单元，其基于请求的类型和所保护的属性来控制对明文信息的访问。

公开(公告)号：US20050121761A1

公开(公告)日：2005-06-09

申请号：US11035986

申请日：2005-01-18

申请人： Kenji Maeda ,  Takashi Takata ,  Takao Ochi ,  Hiroki Naraoka ,  Takeshi Kawabata ,  Yoshiyuki Arai ,  Shigeru Nonoyama ,  Hajime Homma

发明人： Kenji Maeda ,  Takashi Takata ,  Takao Ochi ,  Hiroki Naraoka ,  Takeshi Kawabata ,  Yoshiyuki Arai ,  Shigeru Nonoyama ,  Hajime Homma

IPC分类号： H01L23/12 ,  H01L21/56 ,  H01L21/98 ,  H01L23/29 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K1/18 ,  H01L23/02

CPC分类号： H05K1/186 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.

公开(公告)号：US06582991B1

公开(公告)日：2003-06-24

申请号：US09886997

申请日：2001-06-25

申请人： Kenji Maeda ,  Takashi Takata ,  Takao Ochi ,  Hiroki Naraoka ,  Takeshi Kawabata ,  Yoshiyuki Arai ,  Shigeru Nonoyama ,  Hajime Homma

发明人： Kenji Maeda ,  Takashi Takata ,  Takao Ochi ,  Hiroki Naraoka ,  Takeshi Kawabata ,  Yoshiyuki Arai ,  Shigeru Nonoyama ,  Hajime Homma

IPC分类号： H01L2144

CPC分类号： H05K1/186 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.

公开(公告)号：US06511417B1

公开(公告)日：2003-01-28

申请号：US09387859

申请日：1999-09-01

申请人： Akira Taniguchi ,  Chieko Aizawa ,  Yasuhiro Yoshizawa ,  Fumiyuki Onoda ,  Seiki Toriyama ,  Takeshi Kawabata ,  Katsuyoshi Sasagawa ,  Sumihiro Uchimura ,  Masanao Hara ,  Kazutaka Tsuji ,  Takayasu Miyagi ,  Hiroki Moriyama ,  Hiroshi Ishii ,  Yoshinao Oaki ,  Tsugio Okazaki ,  Jun Hasegawa ,  Yasuo Hirata ,  Tetsuo Nonami

发明人： Akira Taniguchi ,  Chieko Aizawa ,  Yasuhiro Yoshizawa ,  Fumiyuki Onoda ,  Seiki Toriyama ,  Takeshi Kawabata ,  Katsuyoshi Sasagawa ,  Sumihiro Uchimura ,  Masanao Hara ,  Kazutaka Tsuji ,  Takayasu Miyagi ,  Hiroki Moriyama ,  Hiroshi Ishii ,  Yoshinao Oaki ,  Tsugio Okazaki ,  Jun Hasegawa ,  Yasuo Hirata ,  Tetsuo Nonami

IPC分类号： A61B100

CPC分类号： A61B1/31 ,  A61B1/005 ,  A61B1/05 ,  A61B5/06 ,  A61B5/064 ,  A61B5/7257 ,  A61B34/20 ,  A61B90/36 ,  A61B90/361 ,  A61B2034/2051 ,  A61B2034/2072

摘要： An endoscope shape detection system has a CPU included in a control unit. The CPU performs frequency sampling on digital data to calculate coordinates indicating the spatial positions of source coils incorporated in an insertion unit of an endoscope and of marker coils. An inserted state of the insertion unit of the endoscope is estimated based on the calculated coordinate data indicating the positions of the source coils. Display data based on which shape of the endoscope depicted is produced from the calculated coordinate data indicating the positions of the source coils, and output to a video RAM. Display data based on which marker coils are depicted is produced from the calculated coordinate data indicating the positions of the marker coils, and output to the video RAM. Consequently, the positions of the markers are depicted together with the shape of the endoscope. The positional relationship between the insertion unit of the endoscope and a patient's body can therefore be ascertained.

摘要翻译： 内窥镜形状检测系统具有包括在控制单元中的CPU。 CPU对数字数据执行频率采样，以计算指示结合在内窥镜的插入单元中的源极线圈和标记线圈的空间位置的坐标。 基于计算出的表示源极线圈的位置的坐标数据来估计内窥镜的插入单元的插入状态。 根据计算出的表示源极线圈的位置的坐标数据，生成所描绘的内窥镜的形状的显示数据，并输出到视频RAM。 根据计算出的表示标记线圈的位置的坐标数据产生基于标记线圈的显示数据，并输出到视频RAM。 因此，标记的位置与内窥镜的形状一起被描绘。 因此可以确定内窥镜的插入单元与患者身体之间的位置关系。