公开(公告)号：US07214982B2

公开(公告)日：2007-05-08

申请号：US10959223

申请日：2004-10-07

申请人： Yoshinori Kumura ,  Iwao Kunishima ,  Tohru Ozaki

发明人： Yoshinori Kumura ,  Iwao Kunishima ,  Tohru Ozaki

IPC分类号： H01L27/108

CPC分类号： H01L29/945 ,  H01L27/11502 ,  H01L27/11507 ,  H01L29/66181

摘要： A semiconductor device including a ferroelectric random access memory, which has a structure suitable for miniaturization and easy to manufacture, and having less restrictions on materials to be used, comprises a field effect transistor formed on a surface area of a semiconductor wafer, a trench ferroelectric capacitor formed in the semiconductor wafer in one source/drain of the field effect transistor, wherein one electrode thereof is connected to the source/drain, and a wiring formed in the semiconductor wafer and connected to the other electrode of the trench ferroelectric capacitor.

摘要翻译： 包括具有适于小型化并易于制造并且对材料使用限制较少的结构的铁电随机存取存储器的半导体器件包括形成在半导体晶片的表面区域上的场效应晶体管，沟槽铁电体 电容器形成在场效应晶体管的一个源极/漏极中的半导体晶片中，其中一个电极连接到源极/漏极，以及形成在半导体晶片中并连接到沟槽铁电电容器的另一个电极的布线。

公开(公告)号：US20070045687A1

公开(公告)日：2007-03-01

申请号：US11288204

申请日：2005-11-29

申请人： Yoshinori Kumura ,  Tohru Ozaki ,  Susumu Shuto ,  Yoshiro Shimojo ,  Iwao Kunishima

发明人： Yoshinori Kumura ,  Tohru Ozaki ,  Susumu Shuto ,  Yoshiro Shimojo ,  Iwao Kunishima

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65

摘要： A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric capacitor formed above the transistor and comprising a lower electrode, a ferroelectric film and an upper electrode, a first hydrogen barrier film formed over the ferroelectric capacitor, an insulator formed over the first hydrogen barrier film, a contact plug disposed in the insulator and electrically connected with the upper electrode, a second hydrogen barrier film disposed between the contact plug and the insulator continuously, and a wiring connected with the contact plug.

摘要翻译： 公开了一种包括具有改善的可靠性的铁电电容器的半导体器件。 根据本发明的一个方面，提供了一种半导体器件，包括形成在半导体衬底上的晶体管，形成在晶体管上方的铁电电容器，包括下电极，铁电体膜和上电极，第一氢阻挡膜 形成在所述铁电电容器上，形成在所述第一氢阻挡膜上的绝缘体，设置在所述绝缘体中并与所述上电极电连接的接触插塞，连续地配置在所述接触插塞和所述绝缘体之间的第二氢阻挡膜， 与接触插头。

公开(公告)号：US20060102941A1

公开(公告)日：2006-05-18

申请号：US10986060

申请日：2004-11-12

申请人： Hiroshi Itokawa ,  Koji Yamakawa ,  Tohru Ozaki ,  Yoshinori Kumura ,  Takamichi Tsuchiya ,  Nicolas Nagel ,  Bum-Ki Moon ,  Andreas Hilliger

发明人： Hiroshi Itokawa ,  Koji Yamakawa ,  Tohru Ozaki ,  Yoshinori Kumura ,  Takamichi Tsuchiya ,  Nicolas Nagel ,  Bum-Ki Moon ,  Andreas Hilliger

IPC分类号： H01L29/94

CPC分类号： H01L28/55 ,  G11C11/22 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，设置在半导体衬底上方并包括底电极，顶电极和设置在底电极和顶电极之间的电介质膜的电容器，底电极包括含有 铱，设置在电介质膜和第一导电膜之间并由贵金属膜形成的第二导电膜，设置在电介质膜和第二导电膜之间并由具有钙钛矿结构的金属氧化物膜形成的第三导电膜， 以及设置在所述第一导电膜和所述第二导电膜之间并且包括金属膜和金属氧化物膜中的至少一种的防扩散膜，所述扩散防止膜防止包含在所述第一导电膜中的铱的扩散。

公开(公告)号：US07022531B2

公开(公告)日：2006-04-04

申请号：US10618616

申请日：2003-07-15

申请人： Tohru Ozaki ,  Iwao Kunishima ,  Toyota Morimoto ,  Hiroyuki Kanaya

发明人： Tohru Ozaki ,  Iwao Kunishima ,  Toyota Morimoto ,  Hiroyuki Kanaya

IPC分类号： H01L21/00

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

摘要翻译： 一种半导体存储器件，包括具有形成在半导体衬底上的多个存储晶体管的存储单元块。 存储晶体管包括第一和第二杂质扩散区域以及在它们之间形成的栅极。 多个存储单元也包括在存储单元块中，并且具有连接到第一杂质扩散区的下电极，形成在下电极上的铁电膜和形成在铁电体膜上的第一上电极并连接到第二杂质扩散区 地区。 还包括形成在半导体衬底上并连接到存储单元块的一端的块选择晶体管。 第二上电极也形成为与块选择晶体管相邻并且与存储单元的第一上电极断开连接。

公开(公告)号：US06762065B2

公开(公告)日：2004-07-13

申请号：US10448359

申请日：2003-05-30

申请人： Hiroyuki Kanaya ,  Yasuyuki Taniguchi ,  Tohru Ozaki ,  Yoshinori Kumura

发明人： Hiroyuki Kanaya ,  Yasuyuki Taniguchi ,  Tohru Ozaki ,  Yoshinori Kumura

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L21/31116 ,  H01L21/32136 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/75

摘要： A lower electrode is formed on an insulating film on a semiconductor substrate. A pair of ferroelectric films are formed on the lower electrode separately from each other. An upper electrode is formed on each of the pair of ferroelectric films. A portion of the lower electrode on which the ferroelectric film is formed is thicker than a portion thereof on which the ferroelectric film is not formed. Such a structure is obtained by sequentially depositing the lower electrode, the ferroelectric film, and the upper electrode on the insulating film, forming a mask on the upper-electrode, using this mask to etch the upper-electrode and the ferroelectric film to thereby pattern a pair of upper electrodes and a pair of ferroelectric electrodes, forming such a mask that continuously covers the pair of upper electrodes and the pair of ferroelectric films, and then etching the lower-electrode material film.

摘要翻译： 在半导体衬底上的绝缘膜上形成下电极。 一对铁电体膜分别形成在下电极上。 在一对铁电体膜中的每一个上形成上电极。 形成铁电体膜的下部电极的一部分比不形成强电介质膜的部分厚。 通过使用该掩模在绝缘膜上依次沉积下电极，铁电体膜和上电极，在上电极上形成掩模，以蚀刻上电极和铁电体膜，从而形成图案 一对上电极和一对铁电电极，形成连续地覆盖一对上电极和一对铁电体膜的掩模，然后蚀刻下电极材料膜。

公开(公告)号：US06759251B2

公开(公告)日：2004-07-06

申请号：US10320524

申请日：2002-12-17

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L21/76838 ,  H01L28/55

摘要： A semiconductor device having ferroelectric memory cells has memory cell transistors each including first and second source/drain regions. Plug electrodes are formed in contact with the first and second source/drain regions, respectively. A ferroelectric capacitor is formed on the plug electrode connected to the first source/drain region. The ferroelectric capacitor includes a first lower electrode formed on the plug electrode, a ferroelectric film formed on the first lower electrode, and an upper electrode formed on the ferroelectric film. A second lower electrode is formed on the plug electrode connected to the second source/drain region. Wiring is formed to connect the upper electrode to the corresponding second lower electrode.

摘要翻译： 具有铁电存储单元的半导体器件具有各自包括第一和第二源/漏区的存储单元晶体管。 插塞电极分别形成为与第一和第二源极/漏极区域接触。 在与第一源/漏区连接的插头电极上形成铁电电容器。 铁电电容器包括形成在插头电极上的第一下电极，形成在第一下电极上的铁电膜和形成在铁电体膜上的上电极。 在与第二源/漏区连接的插头电极上形成第二下电极。 形成布线以将上电极连接到相应的第二下电极。

公开(公告)号：US06603161B2

公开(公告)日：2003-08-05

申请号：US09801920

申请日：2001-03-09

申请人： Hiroyuki Kanaya ,  Yasuyuki Taniguchi ,  Tohru Ozaki ,  Yoshinori Kumura

发明人： Hiroyuki Kanaya ,  Yasuyuki Taniguchi ,  Tohru Ozaki ,  Yoshinori Kumura

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L21/31116 ,  H01L21/32136 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/75

摘要： There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.

摘要翻译： 提供一种半导体器件，其具有形成在被绝缘体膜覆盖的半导体衬底上的铁电电容器，其中所述强电介质电容器包括：形成在所述绝缘膜上的底部电极; 形成在底部电极上的铁电体膜; 以及形成在强电介质膜上的顶部电极。 铁电体膜具有两层铁电体膜或三层铁电体膜的层叠结构。 上部铁电膜被金属化，并防止氢在下部铁电层中扩散。 堆叠的铁电体膜的晶粒优选不同。

公开(公告)号：US06448618B1

公开(公告)日：2002-09-10

申请号：US09640707

申请日：2000-08-18

申请人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumesa Sunouchi

发明人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumesa Sunouchi

IPC分类号： H01L27108

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/108 ,  Y10S257/90

摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

摘要翻译： 在DRAM中，基于最小设计规则，在半导体衬底上的单元区域中形成多个第一MOSFET，并且在侧壁部分上形成具有侧壁绝缘膜的第一栅极侧壁 每个第一MOSFET的第一栅电极。 在半导体衬底上的外围电路区域中形成至少一个第二MOSFET，并且在第二MOSFET的第二栅电极的侧壁部分上形成具有侧壁绝缘膜的第二栅极侧壁。 能够形成与第一栅电极自对准的精细接触孔的第一MOSFET和能够在抑制短沟道效应的同时充分减轻寄生电阻的第二MOSFET同时形成 基质。

公开(公告)号：US5899739A

公开(公告)日：1999-05-04

申请号：US714405

申请日：1996-09-16

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L27/10852 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10861

摘要： A method of manufacturing a semiconductor device. First, a plurality of wires are arranged in parallel to one another, on a semiconductor substrate. Then, insulating films of a first group are formed on tops of the wires, respectively. Next, second insulating films of a second group are formed on sides of the wires, respectively. Further, among the wires there are formed insulating films of a third group which have upper surfaces located at a level not higher than upper surfaces of the insulating films of the second group. Thereafter, contact holes are formed by subjecting the insulating films of the third group to selectively etching. Finally, the contact holes are filled with electrically conductive material.

公开(公告)号：US5753526A

公开(公告)日：1998-05-19

申请号：US603069

申请日：1996-02-20

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10864

摘要： A method of manufacturing process of a semiconductor device, including the steps of forming a plurality of first trenches in a checkered configuration in a substrate, each of the first trenches having an opening; introducing a first conductivity type impurity from a surface of the substrate so as to form a first conductivity type well in a upper portion of the substrate; forming a capacitor insulating film on a surface of each of the first trenches and burying a storage electrode in each of the first trenches so as to form a trench capacitor in each of the first trenches; burying a first silicon film on each of the storage electrodes of the trench capacitors in the first trenches, etching back each of portions of the first silicon film and removing each of portions of the capacitor insulating films so as to expose portions of side surfaces of the first conductivity type well facing the first trenches; burying a second silicon film doped with a second conductivity type impurity in each of concave portions surrounded by the first silicon films and exposing side surfaces of the first conductivity type well facing the first trenches, and introducing second conductivity type impurities to the first conductivity type well so as to form source regions; and burying a first insulation material on the first and second silicon films in each of the first trenches.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在衬底中形成多个第一沟槽，每个第一沟槽均具有开口; 从所述基板的表面引入第一导电型杂质，以在所述基板的上部形成良好的第一导电型; 在每个第一沟槽的表面上形成电容器绝缘膜，并在每个第一沟槽中埋设存储电极，以在每个第一沟槽中形成沟槽电容器; 在第一沟槽中的沟槽电容器的每个存储电极上埋入第一硅膜，蚀刻第一硅膜的每个部分并去除电容器绝缘膜的每个部分，以暴露出第一硅膜的侧表面的部分 第一导电类型井面对第一沟槽; 在由第一硅膜围绕的每个凹部中埋入掺杂有第二导电类型杂质的第二硅膜，并暴露出面向第一沟槽的第一导电类型的侧表面，并将第二导电类型杂质引入第一导电类型阱 以形成源区; 以及在所述第一沟槽的每一个中的第一和第二硅膜上埋设第一绝缘材料。