公开(公告)号：US20080266939A1

公开(公告)日：2008-10-30

申请号：US12213505

申请日：2008-06-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/02

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US6163046A

公开(公告)日：2000-12-19

申请号：US795408

申请日：1997-02-05

申请人： Yoshinori Okumura ,  Masayoshi Shirahata

发明人： Yoshinori Okumura ,  Masayoshi Shirahata

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/10852

摘要： Provided are a semiconductor device which can prevent occurrence of inconvenience caused by overetching resulting from difference between depths of contact holes simultaneously formed in a memory cell part and a peripheral circuit part and inconvenience resulting from extreme increase of an aspect ratio of the contact holes, and a method of fabricating the same. An aluminum wire (22) provided on an interlayer insulating film (20) of a peripheral circuit part is electrically connected with semiconductor diffusion regions, i.e., N.sup.+ -type source/drain regions (91, 92) (first semiconductor regions) and P.sup.+ -type source/drain regions (81, 82) (second semiconductor regions) by a bit line contact hole (12) formed through the interlayer insulating film (11) to have a buried layer (25) therein and an aluminum wire contact hole (21B) formed through other interlayer insulating films (14, 20) to have a buried layer (27) therein.

摘要翻译： 提供一种半导体器件，其可以防止由存储单元部分和周边电路部分中同时形成的接触孔深度之间的差异导致的过蚀刻引起的不便，以及由于接触孔的纵横比的极大增加而导致的不便， 其制造方法。 设置在外围电路部分的层间绝缘膜（20）上的铝线（22）与半导体扩散区域电连接，即N +型源极/漏极区域（91,92）（第一半导体区域）和P + 通过层间绝缘膜（11）形成的位线接触孔（12）形成有漏极区域（81,82）（第二半导体区域），在其中具有掩埋层（25），铝线接触孔 ）通过其它层间绝缘膜（14,20）形成，以在其中具有掩埋层（27）。

公开(公告)号：US5627093A

公开(公告)日：1997-05-06

申请号：US463809

申请日：1995-06-05

申请人： Atsushi Hachisuka ,  Yoshinori Okumura

发明人： Atsushi Hachisuka ,  Yoshinori Okumura

IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/532 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  H01L29/43 ,  H01L29/49 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/76897 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/53271 ,  H01L27/10873 ,  H01L29/4983 ,  H01L2924/0002

摘要： An electrode wiring layer of a semiconductor device according to this invention includes a first conductive portion formed of polycrystalline silicon or the like, and second conductive portions formed as refractory metal silicide layers on opposite lateral walls of the first conductive portion. Upper surfaces and lateral surfaces thereof are coated with insulating layers formed in separate processes. The insulating layers covering the lateral surfaces in particular are formed by a self-aligning technique requiring no mask process. Where conductive layers are formed over the wiring layer according to this invention, a film forming and patterning process for insulating the conductive portions of the wiring layer is omitted and insulation of the wiring layer is secured.

摘要翻译： 根据本发明的半导体器件的电极布线层包括由多晶硅等形成的第一导电部分和在第一导电部分的相对侧壁上形成为难熔金属硅化物层的第二导电部分。 其上表面和侧表面涂覆有分离工艺形成的绝缘层。 覆盖侧表面的绝缘层特别地由不需要掩模处理的自对准技术形成。 在根据本发明的布线层上形成导电层的情况下，省略了用于绝缘布线层的导电部分的成膜和图案化工艺，并且确保了布线层的绝缘。

公开(公告)号：US5280444A

公开(公告)日：1994-01-18

申请号：US851409

申请日：1992-03-13

申请人： Kaoru Motonami ,  Yoshinori Okumura

发明人： Kaoru Motonami ,  Yoshinori Okumura

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00 ,  G11C11/24

CPC分类号： H01L27/10817

摘要： A storage node of a stacked capacitor in a DRAM comprises a first part connected to a source/drain region and a second part protruding upward from a substrate in a vertical wall shape. The second part includes a concave part in the inner part which is removed by etching. Steps are formed on the inner and outer peripheral surfaces of the vertical wall part. The steps are formed by a self-alignment method using a sidewall insulating layer formed by anisotropic etching. Capacitance of the capacitor is increased by forming steps on the surface of the storage node.

摘要翻译： DRAM中层叠电容器的存储节点包括连接到源极/漏极区域的第一部分和从垂直壁形状的基板向上突出的第二部分。 第二部分包括通过蚀刻去除的内部部分中的凹部。 在垂直壁部的内周面和外周面上形成台阶。 该步骤通过使用由各向异性蚀刻形成的侧壁绝缘层的自对准方法形成。 通过在存储节点的表面上形成步骤来增加电容器的电容。

公开(公告)号：US5240872A

公开(公告)日：1993-08-31

申请号：US925148

申请日：1992-08-06

申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

IPC分类号： H01L21/8242 ,  H01L23/485 ,  H01L27/108

CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002

摘要： A semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅极（4）的表面被第一绝缘膜（5）覆盖，左右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

公开(公告)号：US5153689A

公开(公告)日：1992-10-06

申请号：US404528

申请日：1989-09-08

申请人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

发明人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10808 ,  H01L23/53257 ,  H01L2924/0002

摘要： A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

摘要翻译： 半导体存储器件的存储单元包括一个MOS晶体管（3）和一个堆叠电容器（4）。 MOS晶体管的源极/漏极区域（8a，8b）之一连接到位线（2a，2b）。 位线由MOS晶体管的源极/漏极区域到层叠电容器上方的部分的接触部分形成。 位线由具有高熔点的金属，具有高熔点的金属的硅化物或多晶硅化物形成。 由于该材料对于曝光具有低的反射率，因此提高了互连图形化的精度。

公开(公告)号：US4984055A

公开(公告)日：1991-01-08

申请号：US267103

申请日：1988-11-07

申请人： Yoshinori Okumura ,  Atsuhiro Fujii ,  Masao Nagatomo ,  Hiroji Ozaki ,  Wataru Wakamiya ,  Takayuki Matsukawa

发明人： Yoshinori Okumura ,  Atsuhiro Fujii ,  Masao Nagatomo ,  Hiroji Ozaki ,  Wataru Wakamiya ,  Takayuki Matsukawa

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L23/485 ,  H01L23/522 ,  H01L2924/0002

摘要： A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15). Each of the three insulating layers in the triple layer insulation has its hole-defining surface exposed at the contact hole (15) flush with or displaced laterally into the contact hole (15) away from a corresponding hole-defining exposed surface of the next overlying insulating layer.

摘要翻译： 公开了具有多个导电层的半导体器件。 该器件具有在半导体衬底（1）上间隔开形成的第一级导体（9）。 半导体衬底（1）在相邻的第一层导体（9）之间的主表面上设置有杂质扩散区（11）。 由一对氧化物层（12,14）和夹在氧化物层（12,14）之间的氧化硅层（13）形成的三层绝缘体覆盖在其上的半导体衬底（1）和第一层导体（9） 。 形成至少一个接触孔（15），以通过三层绝缘体延伸到半导体衬底（1）中的杂质扩散区域（11）或半导体衬底（1）上的第一级导体（9）中。 在三层绝缘体和接触孔（15）的内周围壁上设置有二级导体（16,17）。 三层绝缘体中的三个绝缘层中的每一个具有其露出在接触孔（15）处的孔限定表面，该接触孔（15）与接触孔（15）平齐地或相对地偏离接触孔（15），远离与下一个上覆的相应的孔限定的暴露表面 绝缘层。

公开(公告)号：US4956692A

公开(公告)日：1990-09-11

申请号：US266704

申请日：1988-11-03

申请人： Hiroji Ozaki ,  Masahiro Yoneda ,  Ikuo Ogoh ,  Yoshinori Okumura ,  Wataru Wakamiya ,  Masao Nagatomo

发明人： Hiroji Ozaki ,  Masahiro Yoneda ,  Ikuo Ogoh ,  Yoshinori Okumura ,  Wataru Wakamiya ,  Masao Nagatomo

IPC分类号： H01L27/10 ,  H01L21/31 ,  H01L21/334 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L29/66181 ,  H01L21/76205 ,  H01L27/10829

摘要： Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.

摘要翻译： 在半导体衬底的主表面上以预定距离形成两个沟槽。 在包括沟槽的内表面的半导体的主表面上依次形成氧化物膜和氮化物膜。 在包括沟槽的内表面的整个表面上形成抗蚀剂之后，将抗蚀剂图案化以在每个沟槽的侧表面上暴露出氮化膜的一部分。 通过使用图案化的抗蚀剂作为掩模去除氮化物膜的暴露部分并施加热氧化。 然后，在沟槽之间的区域上形成隔离氧化膜，并且鸟嘴的端部位于每个沟槽的侧表面上并连接到形成在每个沟槽中的氧化膜。

公开(公告)号：US4906591A

公开(公告)日：1990-03-06

申请号：US283804

申请日：1988-12-06

申请人： Yoshinori Okumura

发明人： Yoshinori Okumura

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L21/32155 ,  H01L21/2257 ,  H01L21/28525 ,  Y10S148/02

摘要： In a method of manufacturing a semiconductor device having an electric contact, semiconductor regions (9) as a source or drain region of a MOS transistor, having a conductivity type opposite to that of a semiconductor substrate (1) are formed selectively on the substrate. An insulating layer (10) is formed on the substrate (1) to expose only a surface of each semiconductor region (9). Impurity ions of the conductivity type opposite to that of the substrate (1) are implanted into the exposed surface of each region (9). After that, a polycrystal silicon layer (13) is formed on the surface of each region (9) implanted with the impurity ions and on the insulating layer (10). Further, impurity ions of the conductivity type opposite to that of the substrate (1) are further implanted into the polycrystal silicon layer (13). The condition of implanting the impurity ions into the polycrystal silicon layer (13) is set by controlling implantation energy to enable the maximum point of concentration distribution of the impurity ions in a direction perpendicular to the surface of the substrate (1) to be distant from a position of the interface between the polycrystal silicon layer (13) and the substrate (1) by a dimension corresponding to a standard deviation of the concentration distribution of the impurity ions toward the polycrystal silicon layer (13).

摘要翻译： 在制造具有电接触的半导体器件的方法中，选择性地在衬底上形成具有与半导体衬底（1）相反的导电类型的作为MOS晶体管的源极或漏极区域的半导体区域（9）。 在衬底（1）上形成绝缘层（10），仅露出每个半导体区域（9）的表面。 与基板（1）相反的导电类型的杂质离子注入每个区域（9）的暴露表面。 之后，在注入了杂质离子的各区域（9）的表面和绝缘层（10）上形成多晶硅层（13）。 此外，与多晶硅层（13）进一步注入与基板（1）相反的导电类型的杂质离子。 将杂质离子注入多晶硅层（13）中的条件是通过控制注入能量来设定的，以使杂质离子在垂直于衬底（1）表面的方向上的最大浓度分布点远离 多晶硅层（13）和基板（1）之间的界面的位置相当于杂质离子朝向多晶硅层（13）的浓度分布的标准偏差的尺寸。

公开(公告)号：US4891327A

公开(公告)日：1990-01-02

申请号：US227841

申请日：1988-08-03

申请人： Yoshinori Okumura

发明人： Yoshinori Okumura

IPC分类号： H01L27/10 ,  H01L21/28 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10844 ,  H01L27/10805

摘要： Impurities of a conductivity type opposite to a semiconductor substrate are ion-implanted utilizing as a mask a resist or the like formed on the major surface of the semiconductor substrate. Impurity regions spaced apart from each other by a predetermined distance are formed by heat treatment. Conductive layers are formed over the respective impurity regions. A conductive material is formed on an exposed semiconductor substrate through an oxide film to cover the conductive layers, and patterned in a predetermined shape. In addition, conductive layers spaced apart form each other by a predetermined distance are formed on the major surface of the semiconductor substrate. Impurities of the conductivity type opposite to that of the semiconductor substrate are ion-implanted into the conductive layers. The impurities included in the conductive layers are diffused into the semiconductor substrate by heat treatment, so that impurity regions spaced apart from each other by a predetermined distance are formed. A conductive material is formed on the exposed semiconductor substrate through an oxide film to cover the conductive layers, and patterned in a predetermined shape.

摘要翻译： 使用与半导体衬底相反的导电类型的杂质作为形成在半导体衬底的主表面上的抗蚀剂等作为掩模进行离子注入。 通过热处理形成彼此间隔开预定距离的杂质区域。 在各个杂质区域上形成导电层。 导电材料通过氧化膜在暴露的半导体衬底上形成以覆盖导电层，并以预定形状图案化。 此外，在半导体衬底的主表面上形成彼此隔开预定距离的导电层。 导电类型与半导体衬底相反的杂质被离子注入到导电层中。 包含在导电层中的杂质通过热处理扩散到半导体衬底中，从而形成彼此隔开预定距离的杂质区。 导电材料通过氧化膜在暴露的半导体衬底上形成以覆盖导电层，并以预定形状图案化。