公开(公告)号：US09891644B1

公开(公告)日：2018-02-13

申请号：US15387678

申请日：2016-12-22

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

Inventor： Xin Ming ,  Tiansheng Li ,  Jun Xu ,  Zhuo Wang ,  Bo Zhang

IPC: G05F1/575 ,  G05F1/563 ,  G05F1/565

CPC classification number: G05F1/575 ,  G05F1/563 ,  G05F1/565

Abstract: A low-dropout regulator, including: a dynamic pole tracking circuit having an active load, a voltage-to-current converter, a current amplifier, a bias circuit, a regulating transistor, a first feedback resistor, a second feedback resistor, and a first capacitor. The dynamic pole tracking circuit includes: a first PMOS, a second PMOS, a first resistor, and a second resistor. The voltage-to-current converter includes: a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, an eighth NMOS, a third PMOS, a fourth PMOS, a seventh PMOS, an eighth PMOS. The current amplifier includes: a fifth PMOS, a sixth PMOS, a ninth NMOS, a tenth NMOS, and a third resistor. The bias circuit includes: a ninth PMOS, a tenth PMOS, an eleventh PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, and a fourth resistor.

公开(公告)号：US09741837B2

公开(公告)日：2017-08-22

申请号：US15209745

申请日：2016-07-13

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA ,  INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC

Inventor： Jinping Zhang ,  Yadong Shan ,  Gaochao Xu ,  Xin Yao ,  Jingxiu Liu ,  Zehong Li ,  Min Ren ,  Bo Zhang

IPC: H01L29/73 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7397 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/4236

Abstract: A bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for carrier storage or field stop, two metal electrodes, and isolating dielectrics. Each MOS structure includes: a body region, a heavily doped source region, a body contact region, and a gate structure. Each gate structure includes: a gate dielectric and a gate conductive material. The two MOS structures are symmetrically disposed on the top surface and the back surface of the substrate drift layer. The heavily doped source region and the body contact region are disposed in the body region and independent from each other, and both surfaces of the heavily doped source region and the body contact region are connected to each of the two metal electrodes. The gate dielectric separates the gate conductive material from a channel region of each of the MOS structures.

公开(公告)号：US08972812B2

公开(公告)日：2015-03-03

申请号：US13929758

申请日：2013-06-27

Applicant: University of Electronic Science and Technology of China

Inventor： Yajuan He ,  Tingting Xia ,  Tao Luo ,  Wubing Gan ,  Bo Zhang

IPC: G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00 ,  G01R31/317

CPC classification number: G01R31/317 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/3869 ,  Y02D10/152 ,  Y02D10/172

Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

Abstract translation: 一种流水线处理器，包括几级的组合逻辑，电压调节器，计数器，比较器和多个级寄存器。 每个级寄存器被布置在组合逻辑的两个相邻级之间。 级寄存器包括触发器，锁存器，异或门和MUX模块。 当寄存器时钟的高电平到来时，触发器在上升沿锁存第一数据，并且锁存器在高电平期间接收第二数据。 由触发器和锁存器锁存的数据分别由XOR门进行比较。 如果它们相同，则XOR门的输出误差为低电平，触发器的输出被传送到下一级。 否则，异或门的输出误差为高电平，并将锁存器的输出传送到下一级。

公开(公告)号：US10862463B1

公开(公告)日：2020-12-08

申请号：US16848864

申请日：2020-04-15

Applicant: University of Electronic Science and Technology of China

Inventor： Zekun Zhou ,  Jianwen Cao ,  Zhuo Wang ,  He Tang ,  Bo Zhang

IPC: H03K19/0185 ,  H03K3/356 ,  H03K3/012 ,  H03K5/134

Abstract: A level shifter includes a power supply rail conversion block, an RS latch and a digital detection block. The power supply rail conversion block comprises a first NLDMOS transistor, a second NLDMOS transistor, a first PLDMOS transistor, a second PLDMOS transistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first inverter. A gate of the first NLDMOS transistor is connected to an input of the first inverter, a drain of the first NLDMOS transistor is connected to a drain of the first PLDMOS transistor; a source of the first NLDMOS transistor and a source of the second NLDMOS are connected to a referenced ground of an LV power supply rail. The digital detection block comprises a second inverter, a third inverter, a first delay chain, a second delay chain, a first NAND gate and a second NAND gate.

公开(公告)号：US10720524B1

公开(公告)日：2020-07-21

申请号：US16536333

申请日：2019-08-09

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Zhengkang Wang ,  Dong Fang ,  Ruidi Wang ,  Bo Zhang

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: A split-gate enhanced power MOS device includes a substrate and an epitaxial layer formed on an upper surface of the substrate. A control gate trench is provided in the epitaxial layer. The control gate trench includes a gate electrode and a split-gate electrode. The gate electrode includes a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode are located in an upper half portion of the control gate trench and are separated by a first dielectric layer. The first gate electrode and the second gate electrode are located above the split-gate electrode and are separated from the split-gate electrode by a second dielectric layer. The first gate electrode and the second gate electrode are separated from a body region in the epitaxial layer by a gate dielectric.

公开(公告)号：US10673426B2

公开(公告)日：2020-06-02

申请号：US16455803

申请日：2019-06-28

Applicant: University of Electronic Science and Technology of China

Inventor： Xin Ming ,  Li Hu ,  Xuan Zhang ,  Su Pan ,  Chunqi Zhang ,  Yao Qin ,  Zhiwen Zhang ,  Yangli Xin ,  Zhuo Wang ,  Bo Zhang

IPC: H03K17/06 ,  H03K17/16 ,  H02M3/07

Abstract: A switch bootstrap charging circuit suitable for a gate drive circuit of a GaN power device includes a high-voltage MOSFET, a low-voltage MOSFET, a high-voltage MOSFET control module, and a low-voltage MOSFET control module. The low-voltage MOSFET is a PMOS transistor, and the source of the low-voltage MOSFET is connected to the power supply voltage. The drain of the high-voltage MOSFET serves as an output terminal of the switch bootstrap charging circuit. The low-voltage MOSFET control module and the high-voltage MOSFET control module generate a gate drive signal of the low-voltage MOSFET and a gate drive signal of the high-voltage MOSFET according to the gate drive signal of the lower power transistor.

公开(公告)号：US10546951B2

公开(公告)日：2020-01-28

申请号：US15774291

申请日：2016-09-17

Applicant: University of Electronic Science and Technology of China ,  Institute of Electronic and Information Engineering of UESTC in Guangdong

Inventor： Min Ren ,  Yuci Lin ,  Chi Xie ,  Zhiheng Su ,  Zehong Li ,  Jinping Zhang ,  Wei Gao ,  Bo Zhang

IPC: H01L29/78 ,  H01L29/423

Abstract: A trench MOS device with improved single event burnout endurance, applied in the field of semiconductor. The device is provided, in an epitaxial layer, with a conductive type semiconductor pillar connected to a source and a second conductive type current-directing region. Whereby, the trajectory of the electron-hole pairs induced by the single event effect is changed and thus avoids the single event burnout caused by the triggering of parasitic transistors, therefore improving the endurance of the single event burnout of the trench MOS device.

公开(公告)号：US10510747B1

公开(公告)日：2019-12-17

申请号：US16140572

申请日：2018-09-25

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Chunlan Lai ,  Linrong He ,  Li Ye ,  Bo Zhang

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/08 ,  H01L21/768 ,  H01L21/3115 ,  H01L21/324

Abstract: A BCD semiconductor device includes devices integrated on a single chip. The devices include a first high voltage nLIGBT device, a second high voltage nLIGBT device, a first high voltage nLDMOS device, a second high voltage nLDMOS device, a third high voltage nLDMOS device, a first high voltage pLDMOS device and low voltage NMOS, PMOS and PNP devices, and a diode device. A dielectric isolation is applied to the high voltage nLIGBT, nLDMOS and pLDMOS devices to realize a complete isolation between the high and low voltage devices. The nLIGBT, nLDMOS, NPN and low voltage NMOS and PMOS are integrated on the substrate of a single chip. The isolation region composed of the dielectric, the second conductivity type buried layer, the dielectric trench, and the first conductivity type implanted region realizes full dielectric isolation of high and low voltage devices. The six types of high voltage transistors have multiple channels.

公开(公告)号：US10146238B2

公开(公告)日：2018-12-04

申请号：US15599484

申请日：2017-05-19

Applicant: University of Electronic Science and Technology of China

Inventor： Zekun Zhou ,  Yao Wang ,  Jianwen Cao ,  Hongming Yu ,  Yunkun Wang ,  Anqi Wang ,  Zhuo Wang ,  Bo Zhang

IPC: G05F1/10 ,  G05F3/02 ,  G05F1/46 ,  G05F3/24 ,  G05F3/16 ,  H02J7/00

Abstract: A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to μT2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of −40° C.˜100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from μW level to nW level and realize low power consumption.

公开(公告)号：US10056452B2

公开(公告)日：2018-08-21

申请号：US15197701

申请日：2016-06-29

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA ,  ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC

Inventor： Zehong Li ,  Wenlong Song ,  Xunyi Song ,  Hongming Gu ,  Youbiao Zou ,  Jinping Zhang ,  Bo Zhang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/263 ,  H01L21/265 ,  H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L21/324

CPC classification number: H01L29/0634 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802

Abstract: A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.