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    METHOD OF PLANARIZING SUBSTRATE SURFACE
    34.
    发明申请
    METHOD OF PLANARIZING SUBSTRATE SURFACE 审中-公开

    公开(公告)号：US20180012771A1

    公开(公告)日：2018-01-11

    申请号：US15678117

    申请日：2017-08-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

    IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

    Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

    Method of planarizing substrate surface
    35.
    发明授权
    Method of planarizing substrate surface 有权

    公开(公告)号：US09773682B1

    公开(公告)日：2017-09-26

    申请号：US15201628

    申请日：2016-07-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

    IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

    Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    37.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 审中-公开
    半导体结构及其工艺

    公开(公告)号：US20160336269A1

    公开(公告)日：2016-11-17

    申请号：US14709500

    申请日：2015-05-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Shu Min Huang ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Pei-Yu Lee ,  Min-Chuan Tsai ,  Chih-Hsun Lin ,  Wu-Sian Sie ,  Jen-Chieh Lin

    IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/7684 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A semiconductor process includes the following steps. A dielectric layer having a recess is formed on a substrate. A barrier layer is formed to cover the recess, thereby the barrier layer having two sidewall parts. A conductive layer is formed on the barrier layer by an atomic layer deposition process, thereby the conductive layer having two sidewall parts. The two sidewall parts of the conductive layer are pulled down. A conductive material fills the recess and has a part contacting the two sidewall parts of the barrier layer protruding from the two sidewall parts of the conductive layer, wherein the equilibrium potential difference between the barrier layer and the conductive layer is different from the equilibrium potential difference between the barrier layer and the conductive material. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

    Abstract translation: 半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成阻挡层以覆盖凹部，由此阻挡层具有两个侧壁部分。 通过原子层沉积工艺在阻挡层上形成导电层，由此导电层具有两个侧壁部分。 导电层的两个侧壁部分被拉下。 导电材料填充凹部，并且具有接触从导电层的两个侧壁部分突出的阻挡层的两个侧壁部分的部分，其中阻挡层和导电层之间的平衡电位差不同于平衡电位差 在阻挡层和导电材料之间。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
    39.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20250096000A1

    公开(公告)日：2025-03-20

    申请号：US18487141

    申请日：2023-10-16

    Applicant: United Microelectronics Corp.

    Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  Jhih Yuan Chen ,  I-Ming Lai ,  Ang Chan ,  Wei Xin Gao ,  Hsiang Chi Chien ,  Hao-Che Hsu ,  Chau Chung Hou ,  Zong Sian Wu

    IPC: H01L21/304 ,  H01L21/306 ,  H01L21/762

    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.

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