公开(公告)号：US20090102021A1

公开(公告)日：2009-04-23

申请号：US11874009

申请日：2007-10-17

申请人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Kuo-Ching Steven Hsu ,  Kai-Ming Ching

发明人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Kuo-Ching Steven Hsu ,  Kai-Ming Ching

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/05552

摘要： An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad.

摘要翻译： 提供一种集成电路结构及其形成方法。 集成电路结构包括基板; 穿过硅基通孔（TSV）延伸到衬底中; 与TSV间隔开的TSV垫; 以及金属线，并且电连接TSV和TSV焊盘。

公开(公告)号：US09312230B2

公开(公告)日：2016-04-12

申请号：US12701868

申请日：2010-02-08

申请人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo

发明人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13147 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A conductive pillar structure for a die includes a passivation layer having a metal contact opening over a substrate. A bond pad has a first portion inside the metal contact opening and a second portion overlying the passivation layer. The second portion of the bond pad has a first width. A buffer layer over the bond pad has a pillar contact opening with a second width to expose a portion of the bond pad. A conductive pillar has a first portion inside the pillar contact opening and a second portion over the buffer layer. The second portion of the conductive pillar has a third width. A ratio of the second width to the first width is between about 0.35 and about 0.65. A ratio of the second width to the third width is between about 0.35 and about 0.65.

摘要翻译： 用于管芯的导电柱结构包括在衬底上具有金属接触开口的钝化层。 接合焊盘在金属接触开口内部具有第一部分，第二部分覆盖钝化层。 接合焊盘的第二部分具有第一宽度。 接合焊盘上的缓冲层具有第二宽度的柱接触开口以暴露接合焊盘的一部分。 导电柱具有在柱接触开口内部的第一部分和缓冲层上的第二部分。 导电柱的第二部分具有第三宽度。 第二宽度与第一宽度的比率在约0.35和约0.65之间。 第二宽度与第三宽度的比率在约0.35和约0.65之间。

公开(公告)号：US08753971B2

公开(公告)日：2014-06-17

申请号：US13427430

申请日：2012-03-22

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L21/44

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.

摘要翻译： 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。

公开(公告)号：US20120178252A1

公开(公告)日：2012-07-12

申请号：US13427430

申请日：2012-03-22

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L21/768

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.

摘要翻译： 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。

公开(公告)号：US20100171223A1

公开(公告)日：2010-07-08

申请号：US12348650

申请日：2009-01-05

申请人： Chen-Cheng Kuo ,  Chih-Hua Chen ,  Ming-Fa Chen ,  Chen-Shien Chen

发明人： Chen-Cheng Kuo ,  Chih-Hua Chen ,  Ming-Fa Chen ,  Chen-Shien Chen

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having one or more through-silicon vias (TSVs) is provided. The TSVs are formed such that sidewalls of the TSVs have a scalloped surface. In an embodiment, the sidewalls of the TSVs are sloped wherein a top and bottom of the TSVs have different dimensions. The TSVs may have a V-shape wherein the TSVs have a wider dimension on a circuit side of the substrate, or an inverted V-shape wherein the TSVs have a wider dimension on a backside of the substrate. The scalloped surfaces of the sidewalls and/or sloped sidewalls allow the TSVs to be more easily filled with a conductive material such as copper.

摘要翻译： 提供了具有一个或多个穿硅通孔（TSV）的半导体器件。 TSV形成为使得TSV的侧壁具有扇形表面。 在一个实施例中，TSV的侧壁是倾斜的，其中TSV的顶部和底部具有不同的尺寸。 TSV可以具有V形，其中TSV在衬底的电路侧具有更宽的尺寸，或者是倒V形，其中TSV在衬底的背面具有更宽的尺寸。 侧壁和/或倾斜侧壁的扇形表面允许TSV更容易地用诸如铜的导电材料填充。

公开(公告)号：US20080296763A1

公开(公告)日：2008-12-04

申请号：US11756347

申请日：2007-05-31

申请人： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

发明人： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC分类号： H01L23/488

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.

摘要翻译： 提供半导体管芯封装。 半导体管芯封装包括以堆叠构造布置的多个管芯。 在下部或中间模具中形成通孔，以允许电连接到上面堆叠的管芯。 下模具面向上放置并具有将下面的半导体部件电耦合到通硅通孔的再分配线。 堆叠在下模具上方的模具可以朝上取向，使得接触焊盘背离下模或翻转，使得接触焊盘面向下模。 堆叠的管芯可以通过引线接合或焊球电耦合到再分配线。 此外，下模具可以在与堆叠的管芯相对的一侧上具有另一组重新分布线，以将通孔重新路由到不同的引脚配置。

公开(公告)号：US08703609B2

公开(公告)日：2014-04-22

申请号：US13175022

申请日：2011-07-01

申请人： Chen-Cheng Kuo ,  Chen Chen-Shien ,  Kai-Ming Ching ,  Chih-Hua Chen

发明人： Chen-Cheng Kuo ,  Chen Chen-Shien ,  Kai-Ming Ching ,  Chih-Hua Chen

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device including providing a substrate having a front surface and a back surface. A masking element is formed on the front surface of the substrate. The masking element includes a first layer having a first opening and a second layer having a second opening of a greater width than the first opening. The second opening is a tapered opening. The method further includes etching a tapered profile via extending from the front surface to the back surface of the substrate using the formed masking element.

摘要翻译： 一种制造半导体器件的方法，包括提供具有前表面和后表面的衬底。 掩模元件形成在基板的前表面上。 掩模元件包括具有第一开口的第一层和具有比第一开口更宽的第二开口的第二层。 第二个开口是锥形开口。 该方法还包括使用形成的遮蔽元件从基板的前表面延伸到背面来蚀刻锥形轮廓。

公开(公告)号：US20110263120A1

公开(公告)日：2011-10-27

申请号：US13175022

申请日：2011-07-01

申请人： Chen-Cheng Kuo ,  Chen Chen-Shien ,  Kai-Ming Ching ,  Chih-Hua Chen

发明人： Chen-Cheng Kuo ,  Chen Chen-Shien ,  Kai-Ming Ching ,  Chih-Hua Chen

IPC分类号： H01L21/768 ,  H01L21/306

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device including providing a substrate having a front surface and a back surface. A masking element is formed on the front surface of the substrate. The masking element includes a first layer having a first opening and a second layer having a second opening of a greater width than the first opening. The second opening is a tapered opening. The method further includes etching a tapered profile via extending from the front surface to the back surface of the substrate using the formed masking element.

摘要翻译： 一种制造半导体器件的方法，包括提供具有前表面和后表面的衬底。 掩模元件形成在基板的前表面上。 掩模元件包括具有第一开口的第一层和具有比第一开口更宽的第二开口的第二层。 第二个开口是锥形开口。 该方法还包括使用形成的遮蔽元件从基板的前表面延伸到背面来蚀刻锥形轮廓。

公开(公告)号：US20090051039A1

公开(公告)日：2009-02-26

申请号：US11844650

申请日：2007-08-24

申请人： Chen-Cheng Kuo ,  Chen Chen-Shien ,  Kai-Ming Ching ,  Chih-Hua Chen

发明人： Chen-Cheng Kuo ,  Chen Chen-Shien ,  Kai-Ming Ching ,  Chih-Hua Chen

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a substrate having a front surface and a back surface is provided. A plurality of interconnect layers are formed on the front surface and have a first surface opposite the front surface of the substrate. A tapered profile via extends from the first surface of the plurality of interconnect layers to the back surface of the substrate. In one embodiment, a insulating layer is formed on the substrate and includes an opening, and wherein the opening includes conductive material providing contact to the tapered profile via.

摘要翻译： 提供了包括具有前表面和后表面的基板的半导体器件。 多个互连层形成在前表面上并具有与基板的前表面相对的第一表面。 锥形轮廓通孔从多个互连层的第一表面延伸到基底的后表面。 在一个实施例中，在衬底上形成绝缘层并且包括开口，并且其中开口包括提供与锥形轮廓通孔接触的导电材料。

公开(公告)号：US07973413B2

公开(公告)日：2011-07-05

申请号：US11844650

申请日：2007-08-24

申请人： Chen-Cheng Kuo ,  Chen Chen-Shien ,  Kai-Ming Ching ,  Chih-Hua Chen

发明人： Chen-Cheng Kuo ,  Chen Chen-Shien ,  Kai-Ming Ching ,  Chih-Hua Chen

IPC分类号： H01L23/52

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a substrate having a front surface and a back surface is provided. A plurality of interconnect layers are formed on the front surface and have a first surface opposite the front surface of the substrate. A tapered profile via extends from the first surface of the plurality of interconnect layers to the back surface of the substrate. In one embodiment, a insulating layer is formed on the substrate and includes an opening, and wherein the opening includes conductive material providing contact to the tapered profile via.

摘要翻译： 提供了包括具有前表面和后表面的基板的半导体器件。 多个互连层形成在前表面上并具有与基板的前表面相对的第一表面。 锥形轮廓通孔从多个互连层的第一表面延伸到基底的后表面。 在一个实施例中，在衬底上形成绝缘层并且包括开口，并且其中开口包括提供与锥形轮廓通孔接触的导电材料。