利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

43 条记录 (耗时 0.022 秒)

    Nanowire varactor diode and methods of making same
    31.
    发明授权
    Nanowire varactor diode and methods of making same 有权
    纳米线变容二极管及其制作方法

    公开(公告)号：US07115971B2

    公开(公告)日：2006-10-03

    申请号：US10806361

    申请日：2004-03-23

    申请人： David Stumbo ,  Jian Chen ,  David Heald ,  Yaoling Pan

    发明人： David Stumbo ,  Jian Chen ,  David Heald ,  Yaoling Pan

    IPC分类号： H01L29/93

    CPC分类号： B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/93 ,  Y10S977/762

    摘要： A nanowire varactor diode and methods of making the same are disclosed. The structure comprises a coaxial capacitor running the length of the semiconductor nanowire. In one embodiment, a semiconductor nanowire of a first conductivity type is deposited on a substrate. An insulator is formed on at least a portion of the nanowire's surface. A region of the nanowire is doped with a second conductivity type material. A first electrical contact is formed on at least part of the insulator and the doped region. A second electrical contact is formed on a non-doped potion of the nanowire. During operation, the conductivity type at the surface of the nanowire inverts and a depletion region is formed upon application of a voltage to the first and second electrical contacts. The varactor diode thereby exhibits variable capacitance as a function of the applied voltage.

    摘要翻译： 公开了一种纳米线变容二极管及其制造方法。 该结构包括运行半导体纳米线长度的同轴电容器。 在一个实施例中，第一导电类型的半导体纳米线沉积在衬底上。 在纳米线表面的至少一部分上形成绝缘体。 纳米线的区域掺杂有第二导电类型的材料。 在绝缘体和掺杂区域的至少一部分上形成第一电接触。 在纳米线的非掺杂药液上形成第二电接触。 在操作期间，纳米线表面的导电类型反转，并且在向第一和第二电触点施加电压时形成耗尽区。 因此，变容二极管作为施加电压的函数呈现可变电容。

    Efficient thermal activation optical switch and method of making the same
    32.
    发明授权
    Efficient thermal activation optical switch and method of making the same 有权
    高效热激活光开关及其制作方法

    公开(公告)号：US06678435B2

    公开(公告)日：2004-01-13

    申请号：US09861120

    申请日：2001-05-18

    申请人： Yaoling Pan ,  Michele Palmieri ,  Richard E. Haven

    发明人： Yaoling Pan ,  Michele Palmieri ,  Richard E. Haven

    IPC分类号： G02B626

    CPC分类号： G02B6/3576 ,  G02B6/3538 ,  G02B6/3546 ,  G02B2006/12145

    摘要： An optical switch having an insulator under a heater element is disclosed. The insulator reduces the heat loss thereby making the switch more efficient. The insulator is fabricated embedded in the underlying substrate on which the heater and the optical intersection are fabricated. A method of fabricating the optical switch having an insulator is disclosed. A trench is etched on the substrate and filled with oxide or other suitable insulating material. Then, the heater and the optical intersection are fabricated above the insulator.

    摘要翻译： 公开了一种在加热器元件下方具有绝缘体的光开关。 绝缘体减少热损失，从而使开关更有效率。 制造的绝缘体嵌入在其上制造加热器和光学交叉点的下面的基板上。 公开了一种制造具有绝缘体的光开关的方法。 在衬底上蚀刻沟槽，并填充有氧化物或其它合适的绝缘材料。 然后，在绝缘体上方制造加热器和光学交叉点。

    THIN FILM STACK WITH SURFACE-CONDITIONING BUFFER LAYERS AND RELATED METHODS
    34.
    发明申请
    THIN FILM STACK WITH SURFACE-CONDITIONING BUFFER LAYERS AND RELATED METHODS 有权
    具有表面调节缓冲层的薄膜堆叠及相关方法

    公开(公告)号：US20140036340A1

    公开(公告)日：2014-02-06

    申请号：US13565688

    申请日：2012-08-02

    申请人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

    发明人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

    IPC分类号： G02B26/00 ,  C23C16/44

    CPC分类号： G02B26/001

    摘要： This disclosure provides systems, methods and apparatus for a thin film stack with surface-conditioning buffer layers. In one aspect, the thin film stack includes a plurality of thin film layers each having a thickness greater than about 10 nm and a plurality of surface-conditioning buffer layers each having a thickness between about 1 nm and about 10 nm. The surface-conditioning buffer layers are alternatingly disposed between the thin film layers. Each of the surface-conditioning buffer layers are formed with the same or substantially the same thickness and composition. In some implementations, the surface-conditioning buffer layers are formed by atomic layer deposition.

    摘要翻译： 本公开提供了具有表面调节缓冲层的薄膜堆叠的系统，方法和装置。 在一个方面，薄膜堆叠包括多个厚度大于约10nm的薄膜层以及各自具有约1nm至约10nm厚度的多个表面调节缓冲层。 表面调节缓冲层交替地设置在薄膜层之间。 每个表面调节缓冲层以相同或基本上相同的厚度和组成形成。 在一些实施方案中，表面调节缓冲层通过原子层沉积形成。

    METHOD AND APPARATUS FOR WAFER-LEVEL SOLDER HERMETIC SEAL ENCAPSULATION OF MEMS DEVICES
    35.
    发明申请
    METHOD AND APPARATUS FOR WAFER-LEVEL SOLDER HERMETIC SEAL ENCAPSULATION OF MEMS DEVICES 审中-公开
    MEMS器件的水平焊缝密封封装的方法和装置

    公开(公告)号：US20130119489A1

    公开(公告)日：2013-05-16

    申请号：US13294831

    申请日：2011-11-11

    申请人： Tallis Y. Chang ,  Yaoling Pan ,  John H. Hong ,  Chong U. Lee

    发明人： Tallis Y. Chang ,  Yaoling Pan ,  John H. Hong ,  Chong U. Lee

    IPC分类号： H01L31/18 ,  H01L31/0203

    CPC分类号： B81C1/00293 ,  B81C2203/0145

    摘要： A plurality of MEMS devices are formed on a substrate, a sacrificial layer is formed to cover each of the MEMS devices and a protective cap layer is formed on the sacrificial layer. A release hole is formed through the protective cap layer to the underlying sacrificial layer, and a releasing agent is introduced through the release hole to remove the sacrificial layer under the protective cap layer and expose a MEMS device. Optionally, the MEMS device can be released with the same releasing agent or, optionally, with a secondary releasing agent. The release hole is solder sealed, to form a hermetic seal of the MEMS device. Optionally, release holes are formed at a plurality of locations, each over a MEMS device and the releasing forms a plurality of hermetic sealed MEMS devices on the wafer substrate, which are singulated to form separate hermetically sealed MEMS devices.

    摘要翻译： 在衬底上形成多个MEMS器件，形成牺牲层以覆盖每个MEMS器件，并且在牺牲层上形成保护帽层。 通过保护盖层形成释放孔到下面的牺牲层，并且通过释放孔引入脱模剂以除去保护盖层下面的牺牲层并暴露MEMS器件。 可选地，MEMS器件可以用相同的脱模剂或任选地与二次释放剂一起释放。 释放孔被焊接密封，以形成MEMS器件的气密密封。 可选地，在多个位置上形成释放孔，每个位置都在MEMS器件上，并且释放在晶片衬底上形成多个密封的MEMS器件，其被单个化以形成分开的密封的MEMS器件。

    Method of fabricating gate configurations for an improved contacts in nanowire based electronic devices
    37.
    发明授权
    Method of fabricating gate configurations for an improved contacts in nanowire based electronic devices 有权
    制造基于纳米线的电子器件中改进接触的栅极配置的方法

    公开(公告)号：US07871870B2

    公开(公告)日：2011-01-18

    申请号：US12703043

    申请日：2010-02-09

    申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco A. Leon ,  Yaoling Pan ,  Linda T. Romano

    发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco A. Leon ,  Yaoling Pan ,  Linda T. Romano

    IPC分类号： H01L21/00 ,  H01L27/108

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

    SELECTIVE PROCESSING OF SEMICONDUCTOR NANOWIRES BY POLARIZED VISIBLE RADIATION
    40.
    发明申请
    SELECTIVE PROCESSING OF SEMICONDUCTOR NANOWIRES BY POLARIZED VISIBLE RADIATION 有权
    通过极化可见辐射选择性处理半导体纳米颗粒

    公开(公告)号：US20080150165A1

    公开(公告)日：2008-06-26

    申请号：US11936590

    申请日：2007-11-07

    申请人： David P. Stumbo ,  Yaoling Pan ,  Costas P. Grigoropoulos ,  Nipun Misra

    发明人： David P. Stumbo ,  Yaoling Pan ,  Costas P. Grigoropoulos ,  Nipun Misra

    IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L21/02 ,  H05B1/00

    CPC分类号： H01L29/0665 ,  B23K26/073 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods, systems, and apparatuses for annealing semiconductor nanowires and for fabricating electrical devices are provided. Nanowires are deposited on a substrate. A plurality of electrodes is formed. The nanowires are in electrical contact with the plurality of electrodes. The nanowires are doped. A polarized laser beam is applied to the nanowires to anneal at least a portion of the nanowires. The nanowires may be aligned substantially parallel to an axis. The laser beam may be polarized in various ways to modify absorption of radiation of the applied laser beam by the nanowires. For example, the laser beam may be polarized in a direction substantially parallel to the axis or substantially perpendicular to the axis to enable different nanowire absorption profiles.

    摘要翻译： 提供了用于退火半导体纳米线并用于制造电气器件的方法，系统和装置。 纳米线沉积在基底上。 形成多个电极。 纳米线与多个电极电接触。 纳米线是掺杂的。 将极化激光束施加到纳米线以退火至少一部分纳米线。 纳米线可以基本上平行于轴线对准。 激光束可以以各种方式被极化，以通过纳米线来改变施加的激光束的辐射的吸收。 例如，激光束可以在基本上平行于轴线或基本上垂直于轴线的方向上极化，以实现不同的纳米线吸收曲线。