公开(公告)号：US20050259492A1

公开(公告)日：2005-11-24

申请号：US11024737

申请日：2004-12-30

申请人： Shinya Fujioka ,  Kotoku Sato

发明人： Shinya Fujioka ,  Kotoku Sato

IPC分类号： G11C11/4193 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4195 ,  G11C11/4197 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C11/40603 ,  G11C11/40615

摘要： A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.

摘要翻译： 提供保持与从外部提供的访问请求相关的信息的解码结果和地址寄存器的命令寄存器，并且在处理电路即芯片控制电路中解码与来自外部的访问请求有关的信息， 一个地址解码器和一个由访问控制电路对应于存储单元阵列中的外部访问请求的操作可以独立地并行执行，从而可以多次输入来自外部的访问请求，并且可以实现流水线操作 解码和对应于存储单元阵列中的外部访问请求的操作，从而使得可以加速对半导体存储器件的访问操作而不引起任何问题。

公开(公告)号：US06947347B2

公开(公告)日：2005-09-20

申请号：US10623544

申请日：2003-07-22

申请人： Shinya Fujioka

发明人： Shinya Fujioka

IPC分类号： G06F1/26 ,  G06F1/32 ,  G11C5/14 ,  G11C11/406 ,  H02M3/07 ,  G11C7/00

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。

公开(公告)号：US20050094480A1

公开(公告)日：2005-05-05

申请号：US11001619

申请日：2004-12-02

申请人： Shinya Fujioka ,  Shinichi Yamada ,  Kotoku Sato ,  Jun Ohno

发明人： Shinya Fujioka ,  Shinichi Yamada ,  Kotoku Sato ,  Jun Ohno

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4193 ,  G11C8/02

CPC分类号： G11C7/1018 ,  G11C7/22 ,  G11C2207/2227

摘要： A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

摘要翻译： 一种用于控制可以以突发模式设置模式寄存器的半导体存储器的方法。 为了在突发模式下设置操作模式，首先将半导体存储器从突发模式（通过掉电模式）改变为非突发模式的待机模式。 然后，当以与非突发模式中使用的相同的预定顺序输入命令时，半导体存储器被改变为模式寄存器设置模式以设置模式寄存器。

公开(公告)号：US06754126B2

公开(公告)日：2004-06-22

申请号：US10106597

申请日：2002-03-27

申请人： Shusaku Yamaguchi ,  Toshiya Uchida ,  Yoshimasa Yagishita ,  Yoshihide Bando ,  Masahiro Yada ,  Masaki Okuda ,  Hiroyuki Kobayashi ,  Kota Hara ,  Shinya Fujioka ,  Waichiro Fujieda

发明人： Shusaku Yamaguchi ,  Toshiya Uchida ,  Yoshimasa Yagishita ,  Yoshihide Bando ,  Masahiro Yada ,  Masaki Okuda ,  Hiroyuki Kobayashi ,  Kota Hara ,  Shinya Fujioka ,  Waichiro Fujieda

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4087 ,  G11C2211/4061 ,  G11C2211/4062

摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

摘要翻译： 形成多个第一存储块和用于再现第一存储块的数据的第二存储块。 当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。 当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。 因此，可以在不被用户识别的情况下进行刷新操作。 即，可以提供用户友好的半导体存储器。

公开(公告)号：US06643809B2

公开(公告)日：2003-11-04

申请号：US09764415

申请日：2001-01-19

申请人： Hiroyoshi Tsuboi ,  Shinya Fujioka

发明人： Hiroyoshi Tsuboi ,  Shinya Fujioka

IPC分类号： G01R328

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： A semiconductor device which has a test mode for testing the semiconductor device, is provided with a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.

摘要翻译： 具有用于测试半导体器件的测试模式的半导体器件被提供有一个电路，该电路基于输入到其中的虚拟命令信号产生第一信号，并产生指示进入相应测试的第二信号 模式或基于地址信号和第一信号从对应的测试模式退出。

公开(公告)号：US06529439B2

公开(公告)日：2003-03-04

申请号：US09789514

申请日：2001-02-22

申请人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

发明人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C5/06

摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

公开(公告)号：US06487137B2

公开(公告)日：2002-11-26

申请号：US09924469

申请日：2001-08-09

申请人： Hiroyoshi Tsuboi ,  Shinya Fujioka ,  Koichi Nishimura

发明人： Hiroyoshi Tsuboi ,  Shinya Fujioka ,  Koichi Nishimura

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C29/50

摘要： A semiconductor memory device which includes at least two memory cell arrays, a sense amplifier shared by the memory cell arrays and at least two transfer gates connected respectively between each of the memory cell arrays and the sense amplifier. The semiconductor memory device further includes a first voltage supplier supplying a first voltage to the transfer gates, and a second voltage supplier supplying a second voltage to the transfer gates, with second voltage being higher than the first voltage.

摘要翻译： 一种半导体存储器件，包括至少两个存储单元阵列，由存储单元阵列共享的读出放大器和分别连接在每个存储单元阵列和读出放大器之间的至少两个传输门。 半导体存储器件还包括向传输栅极提供第一电压的第一电压供应器和向转移栅极提供第二电压的第二电压供应器，其中第二电压高于第一电压。

公开(公告)号：US06256238B1

公开(公告)日：2001-07-03

申请号：US09610856

申请日：2000-07-06

申请人： Takayuki Nagasawa ,  Shinya Fujioka

发明人： Takayuki Nagasawa ,  Shinya Fujioka

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C29/787

摘要： A semiconductor memory device having memory cells, spare memory cells to replace defective memory cells and a decision block. The decision block has a plurality of groups, each of which decides whether an input address is an address which selects a memory cell in the defective memory cells. A signal having a different address expression type of the input address is provided to each of the groups.

摘要翻译： 具有存储单元的半导体存储器件，用于替换有缺陷存储器单元的备用存储器单元和判定块。 判定块具有多个组，每个组决定输入地址是否是选择缺陷存储单元中的存储单元的地址。 向每个组提供具有输入地址的不同地址表达类型的信号。

公开(公告)号：US06185149B2

公开(公告)日：2001-02-06

申请号：US09340147

申请日：1999-06-28

申请人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

发明人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

IPC分类号： G11C800

CPC分类号： G11C7/1018 ,  G11C7/1072

摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.

摘要翻译： 半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。 当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块 长度。 从上述一个或多个存储单元块读取数据。

公开(公告)号：US5986960A

公开(公告)日：1999-11-16

申请号：US910899

申请日：1997-08-13

申请人： Shinya Fujioka ,  Atsushi Hatakeyama

发明人： Shinya Fujioka ,  Atsushi Hatakeyama

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C8/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C11/4082 ,  G11C11/4087 ,  G11C8/10 ,  Y10T307/826

摘要： A semiconductor integrated circuit having a DRAM, or the like, includes a memory cell block containing a plurality of memory cells, and a core circuit portion for selecting and activating a specified memory cell inside the memory cell block, and is constituted so that a step-up voltage is applied to the core circuit portion at the time of an activated state. The semiconductor integrated circuit further includes a step-up voltage lowering unit for lowering the step-up voltage by a predetermined value and a unit for selectively supplying the step-up voltage and an output voltage of the step-up voltage lowering unit to the core circuit portion.

摘要翻译： 具有DRAM等的半导体集成电路包括包含多个存储单元的存储单元块和用于选择和激活存储单元块内的指定存储单元的核心电路部分，并且构成为步骤 在激活状态时，向核心电路部分施加电压。 半导体集成电路还包括用于将升压电压降低预定值的升压降压单元和用于选择性地将升压电压和升压降压单元的输出电压提供给芯的单元 电路部分