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    Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle
    32.
    发明授权
    Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle 有权
    使用可控硅整流器原理操作具有浮体晶体管的半导体存储器件的方法

    公开(公告)号：US08837247B2

    公开(公告)日：2014-09-16

    申请号：US14023246

    申请日：2013-09-10

    申请人： Yuniarto Widjaja

    发明人： Yuniarto Widjaja

    IPC分类号： G11C7/00

    CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2211/4016 ,  H01L29/7841

    摘要： An exemplary semiconductor memory cell is provided to include: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; a gate positioned between the first and second regions; a buried layer region in electrical contact with the floating body region, below the first and second regions, spaced apart from the first and second regions; and a substrate region configured to inject charge into the floating body region to maintain the state of the memory cell; wherein an amount of charge injected into the floating body region is a function of a charge stored in the floating body region.

    摘要翻译： 提供了一种示例性的半导体存储器单元，其包括：浮动体区域，被配置为被充电到指示存储器单元的状态的电平; 与所述浮体区域电接触的第一区域; 与所述浮体区域电接触并与所述第一区域间隔开的第二区域; 位于第一和第二区域之间的门; 与所述浮体区域电接触的第一和第二区域下方的与所述第一和第二区域间隔开的掩埋层区域; 以及衬底区域，被配置为将电荷注入到所述浮体区域中以保持所述存储单元的状态; 其中注入到浮体区域中的电荷量是存储在浮体区域中的电荷的函数。

    Memory cells, memory cell arrays, methods of using and methods of making
    35.
    发明授权
    Memory cells, memory cell arrays, methods of using and methods of making 有权
    存储单元，存储单元阵列，使用方法和制作方法

    公开(公告)号：US08654583B2

    公开(公告)日：2014-02-18

    申请号：US13937612

    申请日：2013-07-09

    申请人： Yuniarto Widjaja

    发明人： Yuniarto Widjaja

    IPC分类号： G11C14/00

    CPC分类号： G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0097 ,  G11C14/0018 ,  G11C14/0045 ,  G11C16/0416 ,  G11C2211/4016 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/1023 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881 ,  H01L45/06 ,  H01L45/144 ,  H01L45/145

    摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

    摘要翻译： 提供半导体存储单元和存储单元阵列在至少一个实施例中，存储单元包括具有顶表面的衬底，该衬底具有选自p型导电类型和n型导电类型的第一导电类型 ; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型，所述第一区域形成在所述基板中并暴露在所述顶表面处; 具有第二导电类型的第二区域，第二区域形成在基板中，与第一区域间隔开并暴露在顶表面处; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 形成在所述第一和第二区域与所述掩埋层之间的体区，所述体区具有第一导电类型; 位于第一和第二区域之间并位于顶部表面之上的门; 以及非易失性存储器，被配置为在从身体区域传送时存储数据。

    Memory Device Having Electrically Floating Body Transistor
    36.
    发明申请
    Memory Device Having Electrically Floating Body Transistor 有权
    具有电浮体晶体管的存储器件

    公开(公告)号：US20130264656A1

    公开(公告)日：2013-10-10

    申请号：US13746523

    申请日：2013-01-22

    申请人： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

    发明人： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

    IPC分类号： H01L29/78 ,  H01L29/70

    CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/1023 ,  H01L27/11524 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/70 ,  H01L29/73 ,  H01L29/7302 ,  H01L29/732 ,  H01L29/7841

    摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

    摘要翻译： 半导体存储单元包括被配置为被充电到指示从至少第一和第二状态中选择的存储单元的状态的电平的浮动体区域。 存储单元的第一区域与浮体区域电接触。 存储单元的第二区域与第一区域间隔开并且还与浮体区域电接触。 门位于第一和第二区之间。 背偏置区域被配置为当存储器单元处于第一和第二状态之一时产生冲击电离，并且背偏置区被配置为当存储单元位于另一个状态时不产生碰撞电离 第一和第二州。

    METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE WITH FLOATING BODY TRANSISTOR USING SILICON CONTROLLED RECTIFIER PRINCIPLE
    38.
    发明申请
    METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE WITH FLOATING BODY TRANSISTOR USING SILICON CONTROLLED RECTIFIER PRINCIPLE 有权
    使用硅控制的整流器原理操作具有浮动体的晶体管的半导体存储器件的方法

    公开(公告)号：US20120113712A1

    公开(公告)日：2012-05-10

    申请号：US13244916

    申请日：2011-09-26

    申请人： Yuniarto Widjaja

    发明人： Yuniarto Widjaja

    IPC分类号： G11C11/34 ,  H01L29/78

    CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2211/4016 ,  H01L29/7841

    摘要： A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region.

    摘要翻译： 提供一种维持半导体动态随机存取存储单元的数据状态的方法，其中存储单元包括由具有选自p型导电型和n型导电型的第一导电类型的材料制成的衬底; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型; 具有第二导电类型的第二区域，第二区域与第一区域间隔开; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 具有第一导电类型的体区; 以及位于第一和第二区域之间并且邻近身体区域的门。