Method and apparatus for providing a low-level interconnect section in an imager device
    31.
    发明申请
    Method and apparatus for providing a low-level interconnect section in an imager device 审中-公开
    在成像器装置中提供低级互连部分的方法和装置

    公开(公告)号:US20090302323A1

    公开(公告)日:2009-12-10

    申请号:US12155455

    申请日:2008-06-04

    IPC分类号: H01L31/112 H01L31/18

    摘要: Imager pixels with low-level interconnect sections, methods of assembling imager pixels with low-level interconnect sections, and systems containing imager pixels with low-level interconnect sections. Imager pixels are formed such that specific interconnections between transistors and other components of an imager array are removed from one or more upper level metallization sections and placed on a low-level interconnect section closer to the photodetector, such that one upper metallization section is eliminated.

    摘要翻译: 具有低级互连部分的成像器像素,使用低级互连部分组装成像器像素的方法,以及包含具有低级互连部分的成像器像素的系统。 成像器像素被形成为使得晶体管和成像器阵列的其他部件之间的特定互连从一个或多个上层金属化部分移除并放置在更靠近光电检测器的低级互连部分上,从而消除一个上部金属化部分。

    Prevention of photoresist scumming
    33.
    发明申请
    Prevention of photoresist scumming 有权
    防止光刻胶浮渣

    公开(公告)号:US20060240340A1

    公开(公告)日:2006-10-26

    申请号:US11471012

    申请日:2006-06-20

    IPC分类号: G03F1/00

    CPC分类号: G03F7/11 G03F7/0045 G03F7/091

    摘要: A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid level, and thus causes resist scumming. An increased acid layer beneath the resist prevents acid diffusion. In one embodiment, the increased acid layer is a layer of spun-on acid or PAG dissolved in aqueous solution. In another embodiment, the increased acid layer is a hard mask material with a PAG or an acid mixed into the material. The high acid content inhibits the diffusion of acid from the photoresist into neighboring layers, and thus substantially reduces photoresist scumming and footing.

    摘要翻译: 使用光酸产生剂(PAG)或酸来降低抗污垢和基底。 酸从光致抗蚀剂扩散到邻居会导致酸水平降低,从而导致抗污垢浮渣。 抗蚀剂下面的增加的酸层防止酸扩散。 在一个实施方案中,增加的酸层是溶解在水溶液中的纺丝酸或PAG层。 在另一个实施方案中,增加的酸层是具有混合到该材料中的PAG或酸的硬掩模材料。 高酸含量抑制酸从光致抗蚀剂扩散到相邻层中,从而基本上减少光致抗蚀剂的浮渣和基底。

    Methods of forming semiconductor constructions
    34.
    发明申请
    Methods of forming semiconductor constructions 有权
    形成半导体结构的方法

    公开(公告)号:US20060205142A1

    公开(公告)日:2006-09-14

    申请号:US11375696

    申请日:2006-03-13

    摘要: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

    摘要翻译: 本发明包括形成氮化硅层的方法。 提供了包括第一质量和第二质量的衬底。 第一质量包括硅,第二质量包含氧化硅。 在第一质量块上形成牺牲层。 当牺牲层超过第一质量时,在第二质量块上形成含氮材料。 在形成含氮材料之后,去除牺牲层。 随后,形成氮化硅层以跨越第一和第二质量块延伸,其中氮化硅层在含氮材料之上。 此外,在第一质量块内提供导电性增强掺杂剂。 本发明还涉及形成电容器结构的方法。

    Semiconductor constructions
    35.
    发明授权
    Semiconductor constructions 有权
    半导体结构

    公开(公告)号:US07095095B2

    公开(公告)日:2006-08-22

    申请号:US10879372

    申请日:2004-06-28

    IPC分类号: H01L23/58

    摘要: The invention includes a semiconductor construction. The construction has a semiconductor material die with a front surface, a back surface in opposing relation to the front surface, and a thickness of less than 400 microns between the front and back surfaces. The construction also has circuitry associated with the die and over the front surface of the die, and a layer touching the back surface of the die. The layer can correspond to getter-inducing material and/or to a stress-inducing material. The layer can have a composition which includes silicon dioxide and/or silicon nitride. The composition can include one or more hydrogen isotopes, and the hydrogen isotopes can have a higher abundance of deuterium than the natural abundance of deuterium.

    摘要翻译: 本发明包括半导体结构。 该结构具有半导体材料模具,其具有前表面,与前表面相对的后表面,并且在前表面和后表面之间的厚度小于400微米。 该结构还具有与管芯相连的电路和管芯前表面上的电路,以及接触管芯背面的层。 该层可以对应于吸气剂诱导材料和/或对应力诱导材料。 该层可以具有包括二氧化硅和/或氮化硅的组成。 该组合物可以包括一种或多种氢同位素,氢同位素可以具有比氘天然丰度更高的氘丰度。

    Semiconductor devices using anti-reflective coatings
    36.
    发明授权
    Semiconductor devices using anti-reflective coatings 有权
    半导体器件采用防反射涂层

    公开(公告)号:US07067894B2

    公开(公告)日:2006-06-27

    申请号:US10684431

    申请日:2003-10-15

    IPC分类号: H01L31/232

    摘要: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material.

    摘要翻译: 公开了使用光刻工艺制造器件的技术。 该方法包括在衬底的表面上提供第一抗反射涂层。 在光刻工艺中使用的光的波长透明的层被提供在第一抗反射涂层上,并且感光材料设置在透明层的上方。 感光材料暴露于包括光的波长的辐射源。 优选地,第一抗反射涂层在基本上整个透明层的下方延伸。 可以选择第一抗反射涂层的复合折射率以使第一抗反射涂层处的吸收最大化,以减少光敏材料的凹陷。

    Low k interlevel dielectric layer fabrication methods
    37.
    发明授权
    Low k interlevel dielectric layer fabrication methods 失效
    低k层间介质层制作方法

    公开(公告)号:US07067414B1

    公开(公告)日:2006-06-27

    申请号:US09536037

    申请日:2000-03-27

    摘要: A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide-comprising inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the dielectric layer, it is exposed to a plasma including oxygen effective to reduce the dielectric constant to below what it was prior to the exposing. A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least patially formed thereon. In a chamber, an inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is plasma-enhanced chemical vapor deposited over the substrate at subatmospheric pressure. After forming the dielectric layer, it is exposed to a plasma including oxygen at subatmospheric pressure effective to reduce the dielectric constant by at least 10% below what it was prior to the exposing. The exposing occurs without removing the substrate from the chamber between the depositing and the exposing, and pressure within the chamber is maintained at subatmospheric pressure between the depositing and the exposing.

    摘要翻译: 低k层间电介质层制造方法包括提供具有至少部分地形成在其上的集成电路的衬底。 包含碳并具有不大于3.5的介电常数的含氧化物的介电层形成在衬底上。 在形成电介质层之后,将其暴露于包含氧的等离子体中,以有效地将介电常数降低到暴露前的介电常数。 低k级间介电层制造方法包括提供具有至少在其上形成的集成电路的衬底。 在室中,包含碳并具有不大于3.5的介电常数的层间电介质层是在低于大气压的压力下沉积在衬底上的等离子体增强的化学气相。 在形成电介质层之后,将其暴露于含有低于大气压的氧气的等离子体,以有效地将介电常数降低至比曝光之前低至少10%。 在沉积和暴露之间不会从基板移除基板而露出曝光,并且室内的压力保持在沉积和曝光之间的低于大气压的压力。

    Method of forming semiconductor constructions
    38.
    发明授权
    Method of forming semiconductor constructions 失效
    形成半导体结构的方法

    公开(公告)号:US07037808B2

    公开(公告)日:2006-05-02

    申请号:US11197151

    申请日:2005-08-03

    IPC分类号: H01L21/322

    摘要: The invention includes a semiconductor construction. The construction has a semiconductor material die with a front surface, a back surface in opposing relation to the front surface, and a thickness of less than 400 microns between the front and back surfaces. The construction also has circuitry associated with the die and over the front surface of the die, and a layer touching the back surface of the die. The layer can correspond to getter-inducing material and/or to a stress-inducing material. The layer can have a composition which includes silicon dioxide and/or silicon nitride. The composition can include one or more hydrogen isotopes, and the hydrogen isotopes can have a higher abundance of deuterium than the natural abundance of deuterium.

    摘要翻译: 本发明包括半导体结构。 该结构具有半导体材料模具,其具有前表面,与前表面相对的后表面,并且在前表面和后表面之间的厚度小于400微米。 该结构还具有与管芯相连的电路和管芯前表面上的电路,以及接触管芯背面的层。 该层可以对应于吸气剂诱导材料和/或对应力诱导材料。 该层可以具有包括二氧化硅和/或氮化硅的组成。 该组合物可以包括一种或多种氢同位素,氢同位素可以具有比氘天然丰度更高的氘丰度。

    Semiconductor Constructions
    40.
    发明申请
    Semiconductor Constructions 失效
    半导体建筑

    公开(公告)号:US20060001066A1

    公开(公告)日:2006-01-05

    申请号:US11203046

    申请日:2005-08-12

    摘要: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

    摘要翻译: 本发明包括形成氮化硅层的方法。 提供了包括第一质量和第二质量的衬底。 第一质量包括硅,第二质量包含氧化硅。 在第一质量块上形成牺牲层。 当牺牲层超过第一质量时,在第二质量块上形成含氮材料。 在形成含氮材料之后,去除牺牲层。 随后,形成氮化硅层以跨越第一和第二质量块延伸,其中氮化硅层在含氮材料之上。 此外,在第一质量块内提供导电性增强掺杂剂。 本发明还涉及形成电容器结构的方法。