公开(公告)号：US10510878B1

公开(公告)日：2019-12-17

申请号：US16007169

申请日：2018-06-13

申请人： Vanguard International Semiconductor Corporation

发明人： Chung-Yen Chien ,  Sheng-Wei Fu ,  Chung-Yeh Lee

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L29/40 ,  H01L21/321 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/765

摘要： A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.

公开(公告)号：US10483271B2

公开(公告)日：2019-11-19

申请号：US15911176

申请日：2018-03-05

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Zih-Song Wang

IPC分类号： H01L27/11556 ,  H01L27/11519 ,  H01L21/765 ,  H01L23/552

摘要： A non-volatile memory structure including memory cells, at least one isolation layer, and at least one shield electrode is provided. The memory cells are disposed on a substrate. The isolation layer is located between the memory cells. The shield electrode is disposed on the isolation layer and electrically connected to a source line.

公开(公告)号：US10475698B2

公开(公告)日：2019-11-12

申请号：US15475544

申请日：2017-03-31

申请人： Teresa Oh

发明人： Teresa Oh

IPC分类号： H01L21/00 ,  H01L29/00 ,  H01L21/765 ,  H01L29/40 ,  G01N27/414

摘要： Disclosed are an ambipolar transistor and a high-sensitivity electronic sensor using the same. The ambipolar transistor includes: a substrate; a gate formed on the substrate; a gate insulating film formed of an SiOC thin film and disposed on the substrate and the gate; and a source portion and a drain portion formed on the gate insulating film and spaced apart from each other, wherein the source portion and the drain portion comprise: a main source terminal and a main drain terminal disposed on the gate insulating film at right and left sides of the gate, respectively; and a plurality of source sub-terminals and a plurality of drain sub-terminals alternately arranged between the main source terminal and the main drain terminal, respectively.

公开(公告)号：US20190237553A1

公开(公告)日：2019-08-01

申请号：US16379442

申请日：2019-04-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： CHEN-HUA YU ,  MIRNG-JI LII ,  HUNG-YI KUO ,  HAO-YI TSAI ,  TSUNG-YUAN YU ,  MIN-CHIEN HSIAO ,  CHAO-WEN SHIH

IPC分类号： H01L29/40 ,  H01L23/522 ,  H01L21/765

CPC分类号： H01L29/402 ,  H01L21/765 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/562 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/10126 ,  H01L2924/00014

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.

公开(公告)号：US10366916B2

公开(公告)日：2019-07-30

申请号：US15918623

申请日：2018-03-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chihy-Yuan Cheng ,  Chun-Chang Wu ,  Shun-Shing Yang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC分类号： H01L21/84 ,  H01L29/06 ,  H01L21/765 ,  H01L27/088 ,  H01L21/8234

摘要： A semiconductor structure includes a substrate having a first region and a second region being adjacent each other; a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the patterned layer; and a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring includes a first width W1 and is spaced a first distance D1 from the first features, W1 being greater than D1.

公开(公告)号：US10319726B2

公开(公告)日：2019-06-11

申请号：US15642394

申请日：2017-07-06

申请人： Samsung Electronics Co., Ltd.

发明人： In Cheol Nam ,  Sung Hee Han ,  Dae Sun Kim

IPC分类号： H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L21/765 ,  H01L27/108

摘要： A semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into the element isolation region and penetrating the active region, and a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.

公开(公告)号：US20190148389A1

公开(公告)日：2019-05-16

申请号：US16022702

申请日：2018-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei-Cheng Wu ,  Li-Feng Teng ,  Chien-Hung Chang

IPC分类号： H01L27/112 ,  H01L29/06 ,  H01L29/40 ,  H01L21/765 ,  H01L23/00

摘要： A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

公开(公告)号：US20180323192A1

公开(公告)日：2018-11-08

申请号：US15968989

申请日：2018-05-02

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Yong LI

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L21/8234 ,  H01L21/765

CPC分类号： H01L27/0886 ,  H01L21/765 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/404

摘要： A method for fabricating a semiconductor structure includes providing a substrate including isolation regions and a device region between adjacent isolation regions; forming a plurality of fin structures, including a first plurality of fin structures on the isolation regions and a second plurality of fin structures on the device region of the substrate; forming an isolation layer, having a top surface lower than top surfaces of the fin structures, on the substrate between adjacent fin structures; etching the first plurality of fin structures on the isolation regions after forming the isolation layer; and forming a gate structure across the second plurality of fin structures on the device region after etching the first plurality of fin structures formed on the isolation regions. The gate structure covers a portion of sidewall and top surfaces of each fin structure of the second plurality of fin structures on the device region.

公开(公告)号：US20180182754A1

公开(公告)日：2018-06-28

申请号：US15900810

申请日：2018-02-21

申请人： FUJI ELECTRIC CO., LTD.

发明人： Tatsuya NAITO

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L21/765 ,  H01L29/10 ,  H01L29/32

CPC分类号： H01L27/0635 ,  H01L21/76 ,  H01L21/765 ,  H01L27/0727 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/36 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/8611 ,  H01L29/8613

摘要： A semiconductor device that allows easy hole extraction is provided. The semiconductor device includes: a semiconductor substrate having drift and base regions; a transistor portion formed in the semiconductor substrate; and a diode portion formed adjacent to the transistor portion and in the semiconductor substrate. In the transistor portion and the diode portion: a plurality of trench portions each arrayed along a predetermined array direction; and a plurality of mesa portions formed between respective trench portions are formed, among the plurality of mesa portions, at least one boundary mesa portion at a boundary between the transistor portion and the diode portion includes a contact region at an upper surface of the semiconductor substrate and having a concentration higher than that of the base region, and an area of the contact region at the boundary mesa portion is greater than an area of the contact region at another mesa portion.

公开(公告)号：US09997617B2

公开(公告)日：2018-06-12

申请号：US13799955

申请日：2013-03-13

申请人： QUALCOMM Incorporated

发明人： Bin Yang ,  Xia Li ,  Periannan Chidambaram

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/765 ,  H01L27/02 ,  H01L21/762 ,  H01L21/8238

CPC分类号： H01L29/6681 ,  H01L21/7624 ,  H01L21/765 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/785

摘要： Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.