公开(公告)号：US20210210450A1

公开(公告)日：2021-07-08

申请号：US17209113

申请日：2021-03-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHUN-LIN LU ,  KAI-CHIANG WU ,  MING-KAI LIU ,  YEN-PING WANG ,  SHIH-WEI LIANG ,  CHING-FENG YANG ,  CHIA-CHUN MIAO ,  HAO-YI TSAI

IPC: H01L23/00 ,  H01L23/498

Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.

公开(公告)号：US20170126047A1

公开(公告)日：2017-05-04

申请号：US14928651

申请日：2015-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： VINCENT CHEN ,  HUNG-YI KUO ,  CHUEI-TANG WANG ,  HAO-YI TSAI ,  CHEN-HUA YU ,  WEI-TING CHEN ,  MING HUNG TSENG ,  YEN-LIANG LIN

IPC: H02J7/02 ,  H02J7/00

CPC classification number: H01L23/66 ,  H01L23/3107

Abstract: A semiconductor structure includes a transceiver configured to communicate with a device, a molding surrounding the transceiver, a via extending through the molding, an insulating layer disposed over the molding, the via and the transceiver, and a redistribution layer (RDL) disposed over the insulating layer and comprising an antenna and a dielectric layer surrounding the antenna, wherein a portion of the antenna is extended through the insulating layer and the molding to electrically connect with the transceiver.

公开(公告)号：US20170103955A1

公开(公告)日：2017-04-13

申请号：US15385100

申请日：2016-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YUNG-PING CHIANG ,  CHAO-WEN SHIH ,  HAO-YI TSAI ,  MIRNG-JI LII

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/02 ,  H01L21/31053 ,  H01L21/56 ,  H01L22/12 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0332 ,  H01L2224/03334 ,  H01L2224/03462 ,  H01L2224/0384 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/11602 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1412 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/92 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/11

Abstract: A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.

公开(公告)号：US20160064338A1

公开(公告)日：2016-03-03

申请号：US14471320

申请日：2014-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHIA-CHUN MIAO ,  YEN-PING WANG ,  HAO-YI TSAI ,  SHIH-WEI LIANG ,  TSUNG-YUAN YU

IPC: H01L23/00 ,  H01L21/78 ,  H01L29/06

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L29/0692 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03

Abstract: A semiconductor device includes a substrate comprising a front surface, side surfaces, a back surface, and a recessed edge between the side surfaces and either the front surface or the back surface, the front surface comprising an active region, the active region comprising at least one contact pad, a polymeric member disposed and contacted with the recessed edge of the substrate, a mold disposed over the front surface of the substrate and the polymeric member, and an interface between the mold and the polymeric member.

Abstract translation: 一种半导体器件包括：衬底，其包括前表面，侧表面，后表面和在侧表面与前表面或后表面之间的凹入边缘，所述前表面包括有源区，所述有源区至少包括 一个接触垫，设置并与基底的凹入边缘接触的聚合物构件，设置在基底和聚合物构件的前表面上的模具，以及模具和聚合物构件之间的界面。

公开(公告)号：US20180061798A1

公开(公告)日：2018-03-01

申请号：US15797623

申请日：2017-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHUN-LIN LU ,  KAI-CHIANG WU ,  MING-KAI LIU ,  YEN-PING WANG ,  SHIH-WEI LIANG ,  CHING-FENG YANG ,  CHIA-CHUN MIAO ,  HAO-YI TSAI

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06051 ,  H01L2224/1134 ,  H01L2224/13012 ,  H01L2224/13026 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/14051 ,  H01L2224/16058 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3512

Abstract: A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface.

公开(公告)号：US20160099223A1

公开(公告)日：2016-04-07

申请号：US14503795

申请日：2014-10-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHEN-CHIH HSIEH ,  HAO-YI TSAI ,  CHAO-WEN SHIH ,  YUNG-PING CHIANG ,  TSUNG-YUAN YU

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/13 ,  H01L21/56 ,  H01L21/565 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.

Abstract translation: 一种制造半导体结构的方法包括：接收包括设置在其上的管芯焊盘的衬底; 在衬底上并围绕芯片焊盘设置钝化; 在聚合物上沉积钝化物; 形成包括细长部分和与所述管芯焊盘接触的通孔部分的后钝化互连（PPI）; 通过模板将金属膏沉积在PPI的细长部分上; 在金属膏上设置导电凸块; 并且在PPI上以及金属膏和导电凸块周围设置模制品。

公开(公告)号：US20160020181A1

公开(公告)日：2016-01-21

申请号：US14333709

申请日：2014-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TSUNG-YUAN YU ,  HAO-YI TSAI ,  CHAO-WEN SHIH ,  WEN-HSIN CHAN ,  CHEN-CHIH HSIEH

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2224/11

Abstract: A semiconductor device includes a substrate defined with a seal ring region and a circuit region, the substrate includes a seal ring structure and an integrated circuit structure, the seal ring structure is disposed in the seal ring region and includes a plurality of stacked conductive layers interconnected by a plurality of via layers, the integrated circuit structure is disposed in the circuit region and includes an active or a passive device; a metal pad disposed over the seal ring region and contacted with the seal ring structure; a passivation layer disposed over the substrate and covering the metal pad; a polymeric layer disposed over the passivation layer and the circuit region; and a molding disposed over the passivation layer and the polymeric layer, wherein the seal ring structure is covered by the molding.

Abstract translation: 半导体器件包括限定有密封环区域和电路区域的衬底，所述衬底包括密封环结构和集成电路结构，所述密封环结构设置在所述密封环区域中，并且包括多个互连的层叠导电层 通过多个通孔层，集成电路结构设置在电路区域中并且包括有源或无源器件; 设置在所述密封环区域上并与所述密封环结构接触的金属垫; 钝化层，设置在所述衬底上并覆盖所述金属焊盘; 设置在所述钝化层和所述电路区域上的聚合物层; 以及设置在钝化层和聚合物层上的模制件，其中密封环结构被模制件覆盖。

公开(公告)号：US20150137355A1

公开(公告)日：2015-05-21

申请号：US14230775

申请日：2014-03-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TSUNG-YUAN YU ,  HAO-YI TSAI ,  CHAO-WEN SHIH ,  HUNG-YI KUO ,  PI-LAN CHANG

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06131 ,  H01L2224/06133 ,  H01L2224/06134 ,  H01L2224/06177 ,  H01L2224/06179 ,  H01L2224/06515 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16106 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric.

Abstract translation: 半导体器件包括包括表面的第一衬底和在衬底的表面上的焊盘阵列，其中焊盘阵列包括位于同一电平上的第一类型焊盘和第二类型焊盘。 半导体器件还包括将第一类型焊盘或第二类型焊盘连接到第二衬底的导电凸块和连接到与第一类型焊盘和位于第一类型焊盘的投影区域内的通孔不同的导电特征的通孔 并且直接接触第一类型垫。 半导体器件还在衬底中具有电介质并且直接接触第二类型衬垫，其中第二类型衬垫浮在电介质上。

公开(公告)号：US20200075516A1

公开(公告)日：2020-03-05

申请号：US16679051

申请日：2019-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： VINCENT CHEN ,  HUNG-YI KUO ,  CHUEI-TANG WANG ,  HAO-YI TSAI ,  CHEN-HUA YU ,  WEI-TING CHEN ,  MING HUNG TSENG ,  YEN-LIANG LIN

IPC: H01L23/66

Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, a plurality of vias extending through the molding, and a RDL disposed over the transceiver and the plurality of vias. In some embodiments, the RDL includes an antenna disposed over and electrically connected to the transceiver, and a dielectric layer surrounding the antenna. In some embodiments, the antenna includes an elongated portion extending over the molding and a via portion electrically connected to the transceiver.

公开(公告)号：US20180047664A1

公开(公告)日：2018-02-15

申请号：US15237410

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TSUNG-YUAN YU ,  HAO-YI TSAI ,  CHAO-WEN SHIH ,  HUNG-YI KUO ,  PI-LAN CHANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A method of manufacturing a semiconductor device includes: receiving a first substrate with a surface; receiving a second substrate; determining a pad array on the surface of the first substrate, wherein the pad array includes a first type pad and a second type pad; forming a via pattern underlying the pad array in the first substrate according to the location of each via, wherein the first type pad in the pad array is directly contacting a via of the via pattern and the second type pad in the pad array is clear of any via of the via pattern; laterally connecting the second type pad with a conductive trace, wherein the conductive trace connects to another via that is same level with the via contacting the first type pad; and disposing a first conductive bump and a second conductive bump between the first substrate and the second substrate.