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1592 条记录 (耗时 0.025 秒)

    Delay locked loop
    31.
    发明授权
    Delay locked loop 有权

    公开(公告)号：US10965291B2

    公开(公告)日：2021-03-30

    申请号：US16836723

    申请日：2020-03-31

    申请人： SK hynix Inc. ,  Korea University Research and Business Foundation

    发明人： Chul Woo Kim ,  Hyun Su Park

    IPC分类号： H03L7/06 ,  H03L7/081 ,  H03L7/085

    摘要： A delay locked loop includes a main delay circuit including a plurality of unit delay lines that generate a plurality of internal clocks by delaying an input clock, delay amounts of the plurality of unit delay lines being adjusted in response to code signals; a sub-delay circuit including a plurality of sub-delay lines that generate a plurality of phase clocks by respectively delaying the input clock and the plurality of internal clocks; a phase detector configured to compare phases of the plurality of phase clocks and provide a phase detection signal according to a result of the comparison; and a digital circuit configured to update the code signals corresponding to the plurality of unit delay lines one by one at a time when the phase detection signal is provided to the digital circuit.

    Clock data recovery circuit and apparatus including the same
    34.
    发明授权
    Clock data recovery circuit and apparatus including the same 有权

    公开(公告)号：US10924119B1

    公开(公告)日：2021-02-16

    申请号：US17000601

    申请日：2020-08-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： Geumyoung Tak

    IPC分类号： H03L7/08 ,  H03L7/085 ,  H03K3/037 ,  H03L7/107 ,  H03L7/199

    摘要： A clock data recovery circuit configured to receive an input data signal that includes an embedded clock signal includes a clock recovery circuit including a phase detector configured to detect a phase of the embedded clock signal and to generate a recovery clock signal from the input data signal based on the detected phase; and a data recovery circuit configured to generate a recovery data signal from the input data signal by using the recovery clock signal. The phase detector includes a sampling latch circuit configured to output a first sample signal and a second sample signal from the input data signal; and an edge detection circuit configured to generate a phase control signal based on the first sample signal and the second sample signal and output the phase control signal in a period in which the second sample signal is output from the sampling latch circuit.

    Phase measurement
    35.
    发明授权
    Phase measurement 有权

    公开(公告)号：US10914772B2

    公开(公告)日：2021-02-09

    申请号：US16002373

    申请日：2018-06-07

    申请人： SOCIONEXT INC.

    发明人： Albert Hubert Dorner ,  Martin Wahle

    IPC分类号： G01R25/08 ,  H03K5/14 ,  H03K5/26 ,  H03L7/085 ,  G01R25/00 ,  H03L7/22 ,  H03L7/08 ,  H03K5/00

    摘要： The present disclosure relates to phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising: a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time; an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; and a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions.

    Detection and management of frequency errors in a reference input clock signal
    37.
    发明授权
    Detection and management of frequency errors in a reference input clock signal 有权

    公开(公告)号：US10908635B1

    公开(公告)日：2021-02-02

    申请号：US16726481

    申请日：2019-12-24

    申请人： Silicon Laboratories Inc.

    发明人： Harihara Subramanian Ranganathan ,  Vivek Sarda

    IPC分类号： G06F1/06 ,  H03L7/099 ,  H03L7/085 ,  H03L7/197 ,  H03L7/089

    摘要： A method for generating a clock signal includes selecting a primary reference clock signal or a secondary reference clock signal as a reference clock signal for a phase-locked loop configured to generate an output clock signal. The method includes generating an indication of whether a failure of the reference clock signal has occurred by monitoring the secondary reference clock signal and a plurality of additional clock signals using the reference clock signal. The failure is determined based on whether a gross failure of the reference clock signal has occurred and if the gross failure has not occurred, further based on whether a quality failure of the reference clock signal has occurred.

    DELAY LOCKED LOOP
    38.
    发明申请
    DELAY LOCKED LOOP 审中-公开

    公开(公告)号：US20200366295A1

    公开(公告)日：2020-11-19

    申请号：US16703748

    申请日：2019-12-04

    申请人： SK hynix Inc. ,  KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

    发明人： Chul Woo KIM ,  Hyun Su PARK

    IPC分类号： H03L7/081 ,  H03L7/085

    摘要： Embodiments disclose a delay locked loop. The delay locked loop including a main delay circuit configured to generate initial clocks by delaying an internal clock, and sub-delay lines configured to generate phase clocks having a phase difference corresponding to a desired initial delay by respectively delaying the internal clock and the initial clocks. The phase difference among the phase clocks may be adjusted according to delay values of the sub-delay lines.

    Phase to digital converter
    39.
    发明授权
    Phase to digital converter 有权

    公开(公告)号：US10819355B1

    公开(公告)日：2020-10-27

    申请号：US16580117

    申请日：2019-09-24

    申请人： NXP USA, Inc.

    发明人： Firas N. Abughazaleh ,  David Bearden ,  James Andrew Welker ,  Huy Nguyen ,  Venkatarama Mohanareddy Mooraka

    IPC分类号： H03L7/00 ,  H03L7/099 ,  H03L7/085

    摘要： A phase to digital converter (PDC) generates a digital output that represents a phase difference between first and second clocks. The PDC includes a gated ring oscillator (GRO), which includes N signal delay elements coupled together in a ring via a logic gate, wherein a 1st signal delay element of the ring comprises an input coupled to an output of the logic gate, and wherein a Nth signal delay element of the ring comprises an output coupled to a first input of the logic gate. A convertor is coupled to the GRO and configured to generate low order bits of the digital output based on outputs of the logic gate and the N signal delay elements. A first counter includes an input coupled to an output of one of the N signal delay elements or the logic gate, wherein the first counter is configured to generate a first digital counter value. A second counter includes an input coupled to an output of another one of the N signal delay elements or the logic gate, wherein the second counter is configured to generate a second digital counter value. The PDC generates the digital output signal based on the low order bits and one of the first and second digital counter values.