公开(公告)号：US11886234B2

公开(公告)日：2024-01-30

申请号：US17512346

申请日：2021-10-27

申请人： AMBIQ MICRO, INC.

发明人： Scott Hanson

IPC分类号： H02M3/158 ,  G06F1/06 ,  H03L7/18 ,  H03L7/06 ,  H03L7/181 ,  G06F1/3237 ,  G06F1/3287 ,  G06F1/12 ,  G06F11/30 ,  G06F11/34 ,  G06F13/10 ,  G01R19/00 ,  G05F1/56 ,  H03K17/687 ,  H03M1/12 ,  H03L7/00 ,  G05F1/575 ,  G06F1/3296 ,  H02M1/00

CPC分类号： G06F1/06 ,  G01R19/0084 ,  G05F1/56 ,  G05F1/575 ,  G06F1/12 ,  G06F1/3237 ,  G06F1/3287 ,  G06F1/3296 ,  G06F11/3041 ,  G06F11/3414 ,  G06F13/102 ,  H02M3/158 ,  H03K17/687 ,  H03L7/00 ,  H03L7/06 ,  H03L7/18 ,  H03L7/181 ,  H03M1/12 ,  H02M1/0045 ,  Y02B70/10 ,  Y02D10/00

摘要： An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

公开(公告)号：US11329658B2

公开(公告)日：2022-05-10

申请号：US17068275

申请日：2020-10-12

申请人： Wiliot, Ltd.

发明人： Alon Yehezkely

IPC分类号： H03L7/099 ,  H03L7/08 ,  H03B28/00 ,  H03L7/181 ,  H03L7/23

摘要： An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.

公开(公告)号：US11264999B2

公开(公告)日：2022-03-01

申请号：US16816851

申请日：2020-03-12

申请人： Raytheon Company

发明人： William T. Jennings ,  Colby Hoffman ,  Nick Angelo

IPC分类号： G04F10/00 ,  H03L7/181 ,  H03L7/183

摘要： Methods and apparatus for generating phase-shifted clock signals from a reference clock, connecting the phase-shifted clock signals to a counter module so that the phase-shifted clock signals change values in counters in the counter module, and combining the values in the counters to generate an output signal corresponding to an amount of time. One or more events can be detected at a time corresponding to the output signal. In embodiments, pulses can be transmitted and received at a measure time to evaluate connected devices.

公开(公告)号：US11233517B2

公开(公告)日：2022-01-25

申请号：US16918233

申请日：2020-07-01

申请人： MagnaChip Semiconductor, Ltd.

发明人： Yong Sup Lee ,  Gil Sung Roh

IPC分类号： H03L7/06 ,  G06F1/08 ,  H03L7/181

摘要： An auto trimming device includes an oscillator configured to generate an oscillator clock signal, a subtractor configured to receive an expected value for a target frequency and the oscillator clock signal, configured to output a difference value between the expected value and the oscillator clock signal, an index value selector configured to calculate a unit index value using the difference value and configured to detect and output a target index value from the unit index value, an index value register configured to output an oscillator trimming code corresponding to the target index value to the oscillator, and an embedded memory configured to store the oscillator trimming code as a target oscillator trimming code for the target frequency.

公开(公告)号：US20210297081A1

公开(公告)日：2021-09-23

申请号：US17008480

申请日：2020-08-31

申请人： KIOXIA CORPORATION

发明人： Mikio SHIRAISHI

IPC分类号： H03L7/07 ,  H03L7/081 ,  H03L7/181 ,  H03L7/10 ,  H04L25/03

摘要： An equalizer control device includes a first circuit configured to, upon receipt of a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit, output a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other. A second circuit is configured to count the first number during a particular time period based on the output first signal, and select one of equalization parameters to be set to the CTLE circuit based on the counted first number.

公开(公告)号：US11070218B2

公开(公告)日：2021-07-20

申请号：US16851422

申请日：2020-04-17

申请人： Texas Instruments Incorporated

发明人： Ibukun Oluwagbenga Olumuyiwa ,  Nirav Narendrakumar Ginwala

IPC分类号： H03L7/06 ,  H03L7/181 ,  H03L7/099 ,  G06F1/08 ,  H03L7/07

摘要： A system to test a PLL circuit driven by a reference clock includes a first counter coupled to a reference clock output, a first buffer coupled to the first counter, a second counter coupled to a controlled-oscillator (CO) output of the PLL circuit, a second buffer coupled to the second counter, and a processor configured to compute a PLL lock time according to second count values in the second buffer, and to compute a PLL startup slope according to the first count values in the first buffer and the second count values in the second buffer. A method includes powering up a PLL circuit of a wafer, sampling count values of a reference clock and second count values of the PLL circuit and computing a PLL performance parameter according to the sampled count values in a buffer.

公开(公告)号：US20200159279A1

公开(公告)日：2020-05-21

申请号：US16773160

申请日：2020-01-27

申请人： Ambiq Micro, Inc.

发明人： Stephen James Sheafor ,  Scott Hanson ,  Donovan Popps

IPC分类号： G06F1/06 ,  H02M3/158 ,  G06F1/3296 ,  G05F1/575 ,  H03L7/00 ,  H03M1/12 ,  H03K17/687 ,  G05F1/56 ,  G01R19/00 ,  G06F13/10 ,  G06F11/34 ,  G06F11/30 ,  G06F1/12 ,  G06F1/3287 ,  G06F1/3237 ,  H03L7/181 ,  H03L7/06 ,  H03L7/18

摘要： A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

公开(公告)号：US10658019B2

公开(公告)日：2020-05-19

申请号：US14636447

申请日：2015-03-03

申请人： Micron Technology, Inc.

发明人： Jongtae Kwak

IPC分类号： G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  H03L7/081 ,  H03K3/012 ,  H03K3/037 ,  H03L7/181

摘要： A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.

公开(公告)号：US20170302285A1

公开(公告)日：2017-10-19

申请号：US15488676

申请日：2017-04-17

申请人： Rohm Co., Ltd.

发明人： Isao Niwa

IPC分类号： H03L7/099 ,  G11C17/08 ,  H03B5/32 ,  H03L7/181

CPC分类号： H03L7/099 ,  G11C17/08 ,  H03B5/32 ,  H03B5/36 ,  H03L7/146 ,  H03L7/181 ,  H03L7/183 ,  H03L2207/06

摘要： The present invention is related to a clock generating device for generating an internal clock signal having a frequency correlated with a clock frequency of an external oscillator when the clock frequency of the external oscillator is not specified in advance. A clock generating device 105 comprises a memory 134 and a PLL circuit 120. The memory 134 is configured to store information about a frequency of an external clock signal generated by an external oscillator 200 at a predetermined timing. The PLL circuit 120 generates a second clock signal correlated with a first clock signal based on the information stored in the memory 134.

公开(公告)号：US20170041008A1

公开(公告)日：2017-02-09

申请号：US14992057

申请日：2016-01-11

申请人： MEDIATEK Inc.

发明人： Keng-Jan Hsiao ,  Wen-Chi Chao ,  Sheng-Chu Wu ,  Cheng-Yu Chien

IPC分类号： H03L7/08 ,  H03L7/181 ,  H03K3/0231

CPC分类号： H03K3/02315 ,  H03B5/36 ,  H03L1/00 ,  H03L7/08 ,  H03L7/181

摘要： A method and circuitry for generating a trigger signal based on an oscillation signal and associated non-transitory computer program product are provided. The method includes following steps. Firstly, a calibration value is obtained according to a reference frequency and a frequency of the oscillation signal, and a counting value is gradually altered from a first initial value to a breakpoint value. Secondly, the counting value is updated to a second initial value when the counting value is equal to the breakpoint value. Then, the counting value is gradually altered from the second initial value to a final value, and the trigger signal is generated when the counting value is equal to the final value.

摘要翻译： 提供了一种用于基于振荡信号和相关联的非暂时性计算机程序产品产生触发信号的方法和电路。 该方法包括以下步骤。 首先，根据参考频率和振荡信号的频率获得校准值，并且将计数值从第一初始值逐渐改变为断点值。 其次，当计数值等于断点值时，将计数值更新为第二初始值。 然后，计数值从第二初始值逐渐改变为最终值，并且当计数值等于最终值时产生触发信号。