公开(公告)号：US20190221640A1

公开(公告)日：2019-07-18

申请号：US16248092

申请日：2019-01-15

申请人： International Business Machines Corporation

发明人： Alexander Reznicek

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L21/223 ,  H01L29/66 ,  H01L29/08 ,  H01L27/092 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/167 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/265

CPC分类号： H01L29/0673 ,  H01L21/02 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0688 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： A semiconductor device includes a plurality of stacked structures spaced apart from each other on a substrate, wherein the plurality of stacked structures each comprise a plurality of gate layers and a plurality of channel layers, a plurality of arsenic implanted regions on portions of a surface of the substrate adjacent the plurality of stacked structures, and a plurality of epitaxial source/drain regions extending from the plurality of stacked structures, wherein the plurality of epitaxial source/drain regions are spaced apart from the plurality of arsenic implanted regions.

公开(公告)号：US10304938B2

公开(公告)日：2019-05-28

申请号：US15254302

申请日：2016-09-01

申请人： International Business Machines Corporation

发明人： Praneet Adusumilli ,  Hemanth Jagannathan ,  Christian Lavoie

IPC分类号： H01L29/45 ,  H01L21/3215 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/223 ,  H01L21/24 ,  H01L27/092 ,  H01L29/167 ,  H01L29/78 ,  H01L21/285

摘要： Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.

公开(公告)号：US20190157448A1

公开(公告)日：2019-05-23

申请号：US16177434

申请日：2018-11-01

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shinya TAKASHIMA ,  Katsunori UENO ,  Masaharu EDO

IPC分类号： H01L29/78 ,  H01L29/20 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02 ,  H01L21/223 ,  H01L21/324 ,  H01L29/04

摘要： A manufacturing method of a vertical GaN-based semiconductor device having: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type impurity, which is lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, the method includes: implanting an n type dopant in a back surface of the GaN-based semiconductor substrate after forming of the MIS structure, and annealing the GaN-based semiconductor substrate after the implanting of the n type dopant.

公开(公告)号：US10269984B2

公开(公告)日：2019-04-23

申请号：US15741753

申请日：2017-01-25

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

发明人： Jinchao Bai ,  Huibin Guo ,  Xiangqian Ding ,  Jing Wang

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L21/223 ,  H01L29/66 ,  H01L29/417

摘要： The present application discloses A thin film transistor (TFT), including: a substrate; a source-drain layer comprising a source electrode and a drain electrode over the substrate; and an active layer comprising a poly-Si pattern and an amorphous-Si pattern having contact with the poly-Si pattern over the substrate. The amorphous-Si pattern is between the poly-Si pattern and the source-drain layer; the source electrode overlaps with the poly-Si pattern and the amorphous-Si pattern respectively in a direction substantially perpendicular to a surface of the substrate; and the drain electrode overlaps with the poly-Si pattern and the amorphous-Si pattern respectively in the direction substantially perpendicular to the surface of the substrate.

公开(公告)号：US10262864B2

公开(公告)日：2019-04-16

申请号：US15395128

申请日：2016-12-30

申请人： SUNPOWER CORPORATION

发明人： Taiqing Qiu ,  Glyn Jeremy Reynolds ,  Xiao Bai

IPC分类号： H01L21/223 ,  C09D5/24 ,  B01D53/32 ,  B01D53/22 ,  H01L31/18

摘要： Point-of-use enrichment of gas mixtures for semiconductor structure fabrication, and systems for providing point-of-use enrichment of gas mixtures, are described herein. In an example, a system for fabricating a semiconductor structure includes a process chamber for processing a substrate of a semiconductor structure. A gas supply is coupled to the process chamber. A point-of-use gas enrichment module is coupled to the gas supply. The point-of-use gas enrichment module is configured to concentrate a first gas composition to provide a second gas composition to the gas supply for the process chamber. The second gas composition has a relative amount of a hydride species greater than a relative amount of corresponding hydride species in the first gas composition.

公开(公告)号：US20190088520A1

公开(公告)日：2019-03-21

申请号：US15710753

申请日：2017-09-20

申请人： Applied Materials, Inc.

发明人： Philip Allan KRAUS ,  Thai Cheng CHUA ,  Jaeyong CHO

IPC分类号： H01L21/683 ,  H01L21/67 ,  H01L21/02 ,  H01L21/223 ,  H01L21/3065

摘要： A method and apparatus for biasing regions of a substrate in a plasma assisted processing chamber are provided. Biasing of the substrate, or regions thereof, increases the potential difference between the substrate and a plasma formed in the processing chamber thereby accelerating ions from the plasma towards the active surfaces of the substrate regions. A plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that is advantageous for managing uniformity of processing results across the substrate.

公开(公告)号：US20190019892A1

公开(公告)日：2019-01-17

申请号：US16135289

申请日：2018-09-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Wei-Yang Lo ,  Tung-Wen Cheng ,  Chia-Ling Chan ,  Mu-Tsang Lin

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/223

摘要： A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.

公开(公告)号：US10170558B2

公开(公告)日：2019-01-01

申请号：US15782908

申请日：2017-10-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Effendi Leobandung ,  Tenko Yamashita

IPC分类号： H01L21/338 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/223 ,  H01L21/324 ,  H01L29/161 ,  H01L29/78 ,  H01L27/088 ,  H01L29/36

摘要： A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.

公开(公告)号：US10164017B2

公开(公告)日：2018-12-25

申请号：US15887773

申请日：2018-02-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yuichiro Sasaki ,  Bong Soo Kim ,  Tae Gon Kim ,  Yoshiya Moriyama ,  Seung Hyun Song ,  Alexander Schmidt ,  Abraham Yoo ,  Heung Soon Lee ,  Kyung In Choi

IPC分类号： H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/223 ,  H01L21/265

摘要： A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

公开(公告)号：US20180269061A1

公开(公告)日：2018-09-20

申请号：US15976793

申请日：2018-05-10

申请人： Lam Research Corporation

发明人： Reza Arghavani ,  Samantha Tan ,  Bhadri N. Varadarajan ,  Adrien LaVoie ,  Ananda K. Banerji ,  Jun Qian ,  Shankar Swaminathan

IPC分类号： H01L21/223 ,  C23C16/52 ,  H01L21/67 ,  C23C16/455 ,  H01L21/22 ,  H01L21/225 ,  C23C16/04 ,  H01L29/66 ,  C23C16/50

CPC分类号： H01L21/223 ,  C23C16/045 ,  C23C16/45529 ,  C23C16/45544 ,  C23C16/50 ,  C23C16/52 ,  H01L21/2225 ,  H01L21/2252 ,  H01L21/67155 ,  H01L21/67207 ,  H01L29/66803

摘要： Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.