公开(公告)号：US20150091116A1

公开(公告)日：2015-04-02

申请号：US14503460

申请日：2014-10-01

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Patrick Gros D'aillon ,  Michel Marty

IPC: H01L27/146 ,  G02B5/20

CPC classification number: H01L27/14621 ,  G02B5/20 ,  G02B5/281 ,  G02B5/286 ,  G02B5/288 ,  H01L27/14685 ,  H04N9/045

Abstract: A stack of layers defines a filter and is formed by copper on hydrogenated silicon nitride supported by a carrier. The filter includes a layer of hydrogenated silicon nitride, a layer of silicon oxide on the layer of hydrogenated silicon nitride and a layer of copper on the layer of silicon oxide. The layer of hydrogenated silicon nitride may have, in a vicinity of its upper side, a ratio of a number of silicon atoms per cubic centimeter to a number of nitrogen atoms per cubic centimeter lower than 0.8 (or even lower than 0.6), with a number of silicon-hydrogen bonds smaller than or equal to 6×1021 bonds per cubic centimeter (or even smaller than 0.5×1021 bonds per cubic centimeter). The filter further includes an additional layer of copper between the layer of hydrogenated silicon nitride and the carrier.

Abstract translation: 一叠层限定了过滤器，并由由载体支撑的氢化氮化硅上的铜形成。 滤波器包括氢化氮化硅层，氢化氮化硅层上的氧化硅层和氧化硅层上的铜层。 氢化氮化硅层可以在其上侧附近具有每立方厘米的硅原子数与每立方厘米低于0.8（或甚至低于0.6）的氮原子数的比率，其中a 硅 - 氢键的数量小于或等于每立方厘米6×1021键（或甚至小于每立方厘米0.5×1021的键）。 滤波器还包括在氢化氮化硅层和载体之间的附加的铜层。

公开(公告)号：US08994109B2

公开(公告)日：2015-03-31

申请号：US13832373

申请日：2013-03-15

Applicant: Clement Merckling ,  Mario El-Kazzi ,  Guillaume Saint-Girons ,  Guy Hollinger

Inventor： Clement Merckling ,  Mario El-Kazzi ,  Guillaume Saint-Girons ,  Guy Hollinger

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/51 ,  H01L21/02 ,  H01L21/314 ,  H01L29/04 ,  H01L21/316 ,  H01L21/28

CPC classification number: H01L29/045 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02269 ,  H01L21/02293 ,  H01L21/02299 ,  H01L21/28194 ,  H01L21/3147 ,  H01L21/3162 ,  H01L29/513 ,  H01L29/517

Abstract: A method for preparing a multilayer substrate includes the step of deposing an epitaxial γ-Al2O3 Miller index (001) layer on a Si Miller index (001) substrate.

Abstract translation: 制备多层衬底的方法包括在Si Miller指数（001）衬底上去除外延γ-Al 2 O 3 Miller指数（001）层的步骤。

公开(公告)号：US08963210B2

公开(公告)日：2015-02-24

申请号：US13238655

申请日：2011-09-21

Applicant: Rwik Sengupta ,  Rohit Kumar Gupta ,  Mitesh Goyal ,  Olivier Menut

Inventor： Rwik Sengupta ,  Rohit Kumar Gupta ,  Mitesh Goyal ,  Olivier Menut

IPC: H01L23/52 ,  H01L27/118 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/11807 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact.

Abstract translation: 集成电路（IC）单元可以包括第一和第二半导体区域以及在第一和第二半导体区域上方延伸的平行导电线。 IC单元还可以包括电连接到并行导电线的导电线触点，并且可以包括在第一半导体区域和IC单元的对应端之间的至少一个第一线接触，以及至少一个第二线接触 第一半导体区域和第二半导体区域。 相邻的导电线可以分别耦合到至少一个第一线路触点中的一个和至少一个第二线路触点中的一个。

公开(公告)号：US08962399B2

公开(公告)日：2015-02-24

申请号：US14177593

申请日：2014-02-11

Applicant: Commissariat a l'Energie Atomique et aux Ene Alt ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Maud Vinet ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762

CPC classification number: H01L29/66477 ,  H01L21/02236 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/76272 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/1207

Abstract: A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.

Abstract translation: 提供一种用于制造半导体层的半导体层的方法，所述半导体层具有至少两个不同厚度的绝缘体上的半导体层，包括至少一个其上连续设置有绝缘层和第一半导体层的基板，所述方法包括蚀刻第一层 使得所述层是连续的并且包括至少一个具有小于至少一个第二区域的厚度的第一区域; 氧化第一层以在其表面上形成电绝缘氧化膜，使得在第一区域中，氧化膜延伸至绝缘层; 部分地除去氧化膜以露出第一区域外的第一层; 在所述堆叠上形成第二半导体层，以与所述第一层形成具有与所述第一和第二区域的厚度不同的厚度的第三连续半导体层。

公开(公告)号：US20150050001A1

公开(公告)日：2015-02-19

申请号：US14527249

申请日：2014-10-29

Applicant: STMicroelectronics SA

Inventor： Sébastien Pruvost ,  Frederic Gianesello

IPC: H01P3/00

CPC classification number: H01P3/003 ,  H01P3/006 ,  H01P3/082

Abstract: A coplanar waveguide electronic device is formed on a substrate. The waveguide includes a signal ribbon and a ground plane. The signal ribbon is formed of two or more signal lines of a same level of metallization that are electrically connected together. The ground plane is formed of an electrically conducting material which includes rows of holes.

Abstract translation: 在基板上形成共面波导电子器件。 波导包括信号带和接地平面。 信号带由两个或更多个电连接在一起的相同金属化水平的信号线形成。 接地平面由导电材料形成，其包括一排孔。

公开(公告)号：US20150044828A1

公开(公告)日：2015-02-12

申请号：US14453800

申请日：2014-08-07

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Perrine BATUDE ,  Frederic Mazen ,  Benoit Sklenard

IPC: H01L29/786 ,  H01L21/324 ,  H01L21/265

CPC classification number: H01L29/78603 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/1045 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

Abstract: A Method for manufacturing a transistor comprising: a) amorphization and doping, by means of one or more localised implantation(s), of given regions of source and drain blocks based on crystalline semi-conductor material lying on an insulating layer of a semi-conductor on insulator substrate, the implantation(s) being carried out so as to conserve at the surface of said blocks zones of crystalline semi-conductor material on the regions of amorphous semi-conductor material, b) recrystallization of at least one portion of said given regions.

Abstract translation: 一种用于制造晶体管的方法，包括：a）通过位于半导体绝缘层上的晶体半导体材料的源极和漏极区域的给定区域的一个或多个局部注入来非晶化和掺杂， 导体绝缘体衬底上，进行注入以便在非晶半导体材料区域上的结晶半导体材料的所述块区的表面处保存，b）至少一部分所述 给定地区。

公开(公告)号：US08948215B2

公开(公告)日：2015-02-03

申请号：US13449473

申请日：2012-04-18

Applicant: Mounir Zid ,  Alberto Scandurra ,  Carmelo Pistritto ,  Rached Tourki

Inventor： Mounir Zid ,  Alberto Scandurra ,  Carmelo Pistritto ,  Rached Tourki

IPC: H04J3/04 ,  G01R31/08 ,  G11C11/34 ,  H03M9/00

CPC classification number: H03M9/00

Abstract: A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.

Abstract translation: 解串器电路包括解复用器电路，其被配置为从输入端接收串行数据并输出多个划分的数据输出，以及多路复用器电路，被配置为在所述多路复用器电路的第一输入处接收第一逻辑电平，并且在 所述多路复用器电路的第二输入，并在所述多路复用器电路的控制输入处接收所述划分的数据输出之一。 多路复用器电路的输出以并行形式产生接收到的串行数据。

公开(公告)号：US08928340B2

公开(公告)日：2015-01-06

申请号：US13338053

申请日：2011-12-27

Applicant: Philippe Lebourg ,  Paul Armagnat ,  Thomas Droniou

Inventor： Philippe Lebourg ,  Paul Armagnat ,  Thomas Droniou

IPC: G01R31/26 ,  G01R31/3185

CPC classification number: G01R31/318572

Abstract: A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin.

Abstract translation: 用于集成电路的扫描测试的方法包括电路本身执行的以下步骤：在电路接通电源时，观察施加到使用引脚的位序列，其被配置为以外部速率从外部接收串行数据 时钟信号施加到时钟引脚; 当比特序列被识别为测试初始化​​序列时，以测试模式配置电路; 在移位寄存器配置中连接电路的锁存器，并且连接用于从使用引脚串联接收测试矢量的移位寄存器; 将使用引脚的传输方向切换到输出模式，以便以时钟信号的速率提供给外部串行数据; 并将移位寄存器连接到使用引脚上，作为测试结果集合提供其内容。

公开(公告)号：US20140370668A1

公开(公告)日：2014-12-18

申请号：US14177592

申请日：2014-02-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Heimanu NIEBOJEWSKI ,  Yves MORAND ,  Maud VINET

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L21/28123 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

Abstract translation: 本发明涉及一种晶体管的制造方法，其包括制备绝缘体上半导体层的一叠叠层，其中至少一个衬底上依次配置绝缘层和初始半导体层。 该方法包括形成从绝缘层的顶面延伸的至少一个氧化物焊盘，形成由半导体材料制成的附加层，该半导体材料覆盖氧化物焊盘并且旨在形成用于晶体管的沟道，形成栅极 堆叠在氧化物垫的上方，并且在栅极堆叠的任一侧上形成源极和漏极。

公开(公告)号：US08890728B2

公开(公告)日：2014-11-18

申请号：US14179993

申请日：2014-02-13

Applicant: STMicroelectronics SA

Inventor： Nicolas Le Dortz ,  Thierry Simon ,  Pascal Urard ,  Caroline Lelandais-Perrault

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

Abstract: According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M−1 trains involves respectively M−1 second signals gleaned from the derived signal and the suite of M−1 shift coefficients.

Abstract translation: 根据一种实施方式，一种方法包括估计，其一方面包括涉及采样信号的至少一部分的相关处理，从代表时间导数的导出信号中收集的至少一个第一信号的至少一部分 的采样信号和N个部分滤波信号的至少一部分，分别代表在采样信号侧翼的N对包围版本之间的N个加权差，N大于或等于1.另一方面，估计包括矩阵 对该相关处理的结果进行处理。 M-1列车的校正处理涉及从派生信号和一组M-1移位系数收集的M-1个第二信号。