公开(公告)号：US09929253B2

公开(公告)日：2018-03-27

申请号：US15178853

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

公开(公告)号：US09917195B2

公开(公告)日：2018-03-13

申请号：US14812425

申请日：2015-07-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/1033 ,  H01L21/30621 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

公开(公告)号：US09917194B2

公开(公告)日：2018-03-13

申请号：US15365640

申请日：2016-11-30

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

公开(公告)号：US20180070305A1

公开(公告)日：2018-03-08

申请号：US15808592

申请日：2017-11-09

Applicant: STMICROELECTRONICS, INC.

Inventor： Liwen CHU ,  George A. VLANTIS

IPC: H04W52/02 ,  H04W8/22 ,  H04W84/12 ,  H04W88/02 ,  H04W88/08

CPC classification number: H04W52/0209 ,  H04W8/22 ,  H04W52/0206 ,  H04W52/0216 ,  H04W52/0222 ,  H04W52/0229 ,  H04W84/12 ,  H04W88/02 ,  H04W88/08 ,  Y02D70/00 ,  Y02D70/142

Abstract: A IEEE 802.11 Wireless Local Area Network (WLAN) system of an access point (AP) and one or more stations (STAs) reduces power consumption and increases battery life of power efficient low power STAs by decreasing the amount of time that a power efficient low power STA remains in an awake state. After indicating power efficient low power operation during association with an AP supporting such operation, the power efficient low power STA may enter the doze state from the time that the power efficient low power STA sends a PS-Poll until the power efficient low power STA receives the buffered DATA frame from the AP. While implementing the power efficient PS-Poll method, the AP can send the buffered DATA frame to the STA SIFS after the AP sends an ACK to the received PS-Poll from the STA.

公开(公告)号：US20180068902A1

公开(公告)日：2018-03-08

申请号：US15813071

申请日：2017-11-14

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/823807 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

公开(公告)号：US20180061817A1

公开(公告)日：2018-03-01

申请号：US15802525

申请日：2017-11-03

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US09905706B2

公开(公告)日：2018-02-27

申请号：US15260206

申请日：2016-09-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L21/30 ,  H01L29/84 ,  H01H59/00 ,  B82B3/00 ,  H01H1/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306 ,  H01H50/00

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

公开(公告)号：US09899170B2

公开(公告)日：2018-02-20

申请号：US15044762

申请日：2016-02-16

Applicant: STMicroelectronics, Inc.

Inventor： Thomas L. Hopkins

IPC: H02H11/00 ,  H01H35/02 ,  D06F75/26 ,  G05B9/02 ,  H01H35/14

CPC classification number: H01H35/02 ,  D06F75/26 ,  G05B9/02 ,  H01H35/14 ,  H01H2231/012

Abstract: A protective circuit for an apparatus includes an accelerometer having an output and a microcontroller coupled to the output of the accelerometer. The protective circuit also includes a switch for controlling the apparatus coupled to an output of the microcontroller and a load coupled to the switch. A power source is coupled to the load and the switch. In operation the microcontroller is cable of sending a signal to the switch to turn of power to the load when a dangerous condition as detected from the accelerometer data has occurred.

公开(公告)号：US20180049096A1

公开(公告)日：2018-02-15

申请号：US15725011

申请日：2017-10-04

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov ,  Aidan Cully ,  James D. Allen

IPC: H04W40/08 ,  H04L12/801 ,  H04W52/46 ,  H04L12/24 ,  H04W52/02 ,  H04W40/10 ,  H04L12/26

Abstract: In accordance with an embodiment, a network device includes a network controller and at least one network interface coupled to the network controller that includes at least one media access control (MAC) device configured to be coupled to at least one physical layer interface (PHY). The network controller may be configured to determine a network path comprising the at least one network interface that has a lowest power consumption and minimum security attributes of available media types coupled to the at least one PHY.

公开(公告)号：US20180047849A1

公开(公告)日：2018-02-15

申请号：US15723149

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/788 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.