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    Non-volatile memory cells with enhanced channel region effective width, and method of making same
    474.
    发明授权
    Non-volatile memory cells with enhanced channel region effective width, and method of making same 有权
    具有增强的通道区域有效宽度的非易失性存储单元及其制造方法

    公开(公告)号：US09293359B2

    公开(公告)日：2016-03-22

    申请号：US14191625

    申请日：2014-02-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Hieu Van Tran ,  Chien-Sheng Su ,  Prateep Tuntasood

    IPC: H01L29/788 ,  H01L21/762 ,  H01L29/66 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

    Abstract: A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.

    Abstract translation: 一种存储器件阵列，其具有形成在半导体衬底中的间隔开的平行隔离区域，在每对相邻隔离区域之间具有有源区域。 每个隔离区域包括形成在衬底表面中的沟槽和形成在沟槽中的绝缘材料。 绝缘材料的顶表面的部分凹陷在基底的表面下方。 每个有源区域包括一列存储单元，每个存储单元具有间隔开的第一和第二区域，其间具有通道区域，在第一沟道区域部分上的浮动栅极以及在第二沟道区域部分上的选择栅极。 选择栅极形成为垂直于隔离区域延伸的连续字线，并且每个形成用于一行存储器单元的选择栅极。 每个字线的一部分向下延伸到沟槽中并且横向设置成与沟槽的侧壁相邻。

    Split-Gate Flash Memory Cell With Improved Scaling Using Enhanced Lateral Control Gate To Floating Gate Coupling
    476.
    发明申请
    Split-Gate Flash Memory Cell With Improved Scaling Using Enhanced Lateral Control Gate To Floating Gate Coupling 审中-公开
    使用增强型横向控制门到浮动栅极耦合的改进的缩放分离栅极闪存单元

    公开(公告)号：US20160043095A1

    公开(公告)日：2016-02-11

    申请号：US14790540

    申请日：2015-07-02

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Chien-Sheng Su ,  Nhan Do

    IPC: H01L27/115 ,  H01L29/66

    CPC classification number: H01L27/11521 ,  H01L21/823425 ,  H01L21/823475 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

    Abstract translation: 非易失性存储单元包括在第二导电类型的衬底中的第一导电类型的第一和第二间隔开的区域的半导体衬底，以及衬底中的沟道区。 浮动栅极具有垂直设置在沟道区域的第一部分上的第一部分和垂直设置在第一区域上的第二部分。 浮动门包括倾斜的上表面，其以一个或多个尖锐边缘终止。 擦除栅极垂直设置在浮动栅极上，其中一个或多个尖锐边缘面向擦除栅极。 控制门具有横向邻近浮动栅极设置的第一部分，并且垂直地设置在第一区域上。 选择栅极具有垂直设置在沟道区域的第二部分上并且横向邻近浮置栅极的第一部分。

    Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same
    478.
    发明申请
    Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same 审中-公开
    具有绝缘体硅基板的嵌入式存储器件及其制造方法

    公开(公告)号：US20150263040A1

    公开(公告)日：2015-09-17

    申请号：US14216553

    申请日：2014-03-17

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do

    IPC: H01L27/12 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L29/78

    CPC classification number: H01L27/1203 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/1207 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7841 ,  H01L29/7881

    Abstract: A semiconductor device having a silicon substrate with a first area including a buried insulation layer with silicon over and under the insulation layer and a second area in which the substrate lacks buried insulation disposed under any silicon. Logic devices are formed in the first area having spaced apart source and drain regions formed in the silicon that is over the insulation layer, and a conductive gate formed over and insulated from a portion of the silicon that is over the insulation layer and between the source and drain regions. Memory cells are formed in the second area that include spaced apart second source and second drain regions formed in the substrate and defining a channel region therebetween, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region.

    Abstract translation: 一种具有硅衬底的半导体器件，其具有第一区域，该第一区域包括在绝缘层之上和之下的具有硅的掩埋绝缘层，以及第二区域，其中衬底缺少设置在任何硅下的掩埋绝缘体。 逻辑器件形成在第一区域中，其中形成在绝缘层之上的硅中具有间隔开的源极和漏极区域，以及形成在绝缘层之上和源极之间的硅的一部分上并与其绝缘的导电栅极 和漏区。 存储单元形成在第二区域中，该第二区域包括形成在基板中的间隔开的第二源极和第二漏极区域，并且在其间限定沟道区域;布置在沟道区域的第一部分之上并与沟道区域的第一部分绝缘的浮置栅极;以及选择栅极 并且与沟道区域的第二部分绝缘。

    Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same
    480.
    发明申请
    Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same 审中-公开
    具有自对准浮动和擦除门的非易失性存储单元及其制造方法

    公开(公告)号：US20150179749A1

    公开(公告)日：2015-06-25

    申请号：US14133821

    申请日：2013-12-19

    Applicant: Silicon Storage Technology, Inc

    Inventor： Bomy Chen ,  Chien-Sheng Su ,  Nhan Do

    IPC: H01L29/423 ,  H01L29/66 ,  G11C16/10 ,  H01L29/788 ,  H01L27/115

    CPC classification number: H01L29/42328 ,  G11C16/0408 ,  G11C16/10 ,  H01L21/28238 ,  H01L27/11517 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

    Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. The control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. The erase gate is disposed at least partially over and insulated from the floating gate. Any portion of the trench between the pair of floating gates is free of electrically conductive elements except for a lower portion of the erase gate.

    Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，用于控制其导电性。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘，以控制其导电性。 擦除栅极至少部分地设置在浮栅上并与浮栅绝缘。 一对浮动栅极之间的沟槽的任何部分除了擦除栅极的下部以外没有导电元件。

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