公开(公告)号：US20240330048A1

公开(公告)日：2024-10-03

申请号：US18128977

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Efraim ROTEM ,  Stephen H. GUNTHER ,  Rajshree CHABUKSWAR ,  Vishwesh MAGODE RUDRAMUNI ,  Bharath Kumar VEERA ,  Joseph ALBERTS ,  Madhusudan CHIDAMBARAM ,  Zhongsheng WANG ,  Preeti AGARWAL ,  Praveen Kumar GUPTA

IPC: G06F9/48

CPC classification number: G06F9/4893

Abstract: An apparatus and method are described for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores and power management circuitry to associate a plurality of performance values and a plurality of efficiency values with the plurality of cores. In some implementations, each core is associated with at least one performance value and at least one efficiency value. The performance values and efficiency values are used by a scheduler for scheduling threads on the plurality of cores. Some implementations include dynamic core configuration hardware logic coupled to or integral to the power management circuitry to resolve a plurality of configuration requests into a consolidated request for updating one or more performance values of the plurality of performance values and/or one or more efficiency values of the plurality of efficiency values.

公开(公告)号：US20240329995A1

公开(公告)日：2024-10-03

申请号：US18194010

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Scott D. Constable

IPC: G06F9/30 ,  G06F11/10 ,  G06F12/14

CPC classification number: G06F9/3016 ,  G06F11/1004 ,  G06F12/1425 ,  G06F2212/1052

Abstract: Circuitry and methods for implementing one or more predicated capability instructions are described. In certain examples, a hardware processor (e.g., core) includes a capability management circuit to check a capability for a memory access request for a memory, the capability comprising an address field for an address to be accessed by the memory access request and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access; a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising a field to indicate the capability, and an opcode to indicate: an operation to be performed for the address, that an execution circuit is to perform a first check that a condition code, that indicates a status from a previous execution of the execution circuit, is a certain value, that the capability management circuit is to perform a second check that the capability authorizes access to the address, and in response to the first check and the second check both passing, cause the execution circuit to perform the operation for the address; and the execution circuit to execute the decoded single instruction according to the opcode.

公开(公告)号：US20240329793A1

公开(公告)日：2024-10-03

申请号：US18129745

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Aleksander Magi ,  Glen J. Anderson ,  Arvind Kumar ,  Meng Shi

IPC: G06F3/04815 ,  G06V10/94

CPC classification number: G06F3/04815 ,  G06V10/945

Abstract: Technologies for device management in metaverse interactions are disclosed. In an illustrative embodiment, a compute device is connected to remote compute devices in a metaverse. The compute device may detect local devices, such as by seeing a device in images captured by a camera of the compute device. The local device may be, e.g., a cell phone or smartwatch. The local devices may be registered by the compute device and reproduced in the metaverse. The local user of the compute device may interface with the local devices in the metaverse. The local user may allow remote users to interface or control the local device as well.

公开(公告)号：US20240329677A1

公开(公告)日：2024-10-03

申请号：US18192440

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Kosta Luria ,  Michael Zelikson ,  Lior Gil

IPC: G05F1/575 ,  G05F1/565 ,  G05F1/59

CPC classification number: G05F1/575 ,  G05F1/565 ,  G05F1/59

Abstract: Embodiments herein relate to a Digital Linear Voltage Regulator (DLVR). The DLVR includes a set of power links which each includes many columns of power transistors. The columns can be turned on or off individually based on digital data from a main control circuit. Additionally, individual power links can be turned on or off based on monitoring of a dropout voltage of the set of power links and a drain-to-source resistance, Rds_on, of replica columns. An input voltage may be monitored as an alternative. The monitoring compensates for changes in Rds_on due to changes in an input voltage, Vin, which could otherwise result in unstable behavior. The DLVR can avoid the complexity and power losses of dynamic biasing of the control gate voltages of the transistors.

公开(公告)号：US20240329320A1

公开(公告)日：2024-10-03

申请号：US18565319

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Nicholas D. Psaila ,  Richard Laming

IPC: G02B6/30 ,  G02B6/32 ,  G02B6/38

CPC classification number: G02B6/305 ,  G02B6/32 ,  G02B6/3853 ,  G02B6/3885

Abstract: An optical interconnect component for use in transmitting light between a photonic integrated circuit and one or more optical fibres attached to an optical fibre connector ferrule is disclosed. The optical interconnect component comprises a step formed at an edge of the optical interconnect component, the step including a ledge and a facet, one or more optical beam management elements formed in a surface of the optical interconnect component, and a plurality of integrated optical waveguides. Each of two or more of the integrated optical waveguides extends from the facet so as to define a plurality of optical ports at the facet, and each of the one or more optical beam management elements is aligned with, but separated from, an end of a corresponding one of the plurality of integrated optical waveguides. Also disclosed are an optical fibre connector ferrule, an optical interconnect assembly comprising the optical interconnect component and the optical fibre connector ferrule, and an optical system comprising the optical interconnect assembly, a photonic integrated circuit, and one or more optical fibres.

公开(公告)号：US20240329122A1

公开(公告)日：2024-10-03

申请号：US18128617

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Amit PALIWAL ,  Xiao WEN ,  Dipto THAKURTA

IPC: G01R31/28

CPC classification number: G01R31/2884

Abstract: A device under test (DUT) structure for voltage contrast (VC) detection of contact opens comprises a fin formed along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. A trench contact (TCN) segment is along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. A floating gate is generally parallel to the TCN segment over the fin, wherein the floating gate and the TCN segment are not in contact, and the floating gate does not have a via formed thereon.

公开(公告)号：US20240327201A1

公开(公告)日：2024-10-03

申请号：US18192576

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Mohammad Mamunur Rahman ,  Suddhasattwa Nad ,  Sashi Kandanur ,  Darko Grujicic ,  Benjamin Duong ,  Srinivas Pietambaram ,  Tarek Ibrahim ,  Whitney Bryks

IPC: B81B7/00 ,  B81C1/00 ,  G02B6/12

CPC classification number: B81B7/0048 ,  B81C1/00325 ,  G02B6/12004 ,  B81B2201/0228 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2201/03 ,  B81B2201/045 ,  B81B2207/07 ,  B81B2207/096 ,  B81B2207/097

Abstract: MEMS dies embedded in glass cores of integrated circuit (IC) package substrates are disclosed. An example integrated circuit (IC) package includes a package substrate including a glass core, the example integrated circuit (IC) package also includes a micro electromechanical system (MEMS) die positioned in a cavity of the glass core.

公开(公告)号：US12107611B2

公开(公告)日：2024-10-01

申请号：US17119543

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： Ronen Kronfeld ,  Rula Jubran

IPC: H04B1/18 ,  H04B1/00 ,  H04B1/12 ,  H04B1/16

CPC classification number: H04B1/18 ,  H04B1/005 ,  H04B1/12 ,  H04B1/1607

Abstract: Systems and methods of reducing SNR and increasing bandwidth of received signals are disclosed. LNAs receive signals from an antenna via a common input matching network. The amplified signals are downconverted, filtered and digitized before being coherently combined at a DSP. Depending on the LO frequencies used by mixers in the different receiver paths, the combined signals reduce the SNR when the LO frequencies are the same by reducing the non-correlated noise introduced by the LNAs or increase the bandwidth processed when the LO frequencies are different. The bandwidths are contiguous or non-contiguous.

公开(公告)号：US12106815B2

公开(公告)日：2024-10-01

申请号：US17109376

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Ravi Motwani ,  Pranav Kalavade ,  Rohit Shenoy ,  Rifat Ferdous

IPC: G11C16/04 ,  G06F12/0882 ,  G11C29/14 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G06F12/0882 ,  G11C29/14 ,  G11C29/44

Abstract: Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. The first density and the second density are different from one another.

公开(公告)号：US12106104B2

公开(公告)日：2024-10-01

申请号：US17133328

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Christopher J. Hughes

IPC: G06F9/30 ,  G06F12/0862 ,  H03M7/30

CPC classification number: G06F9/30047 ,  G06F9/30145 ,  G06F12/0862 ,  H03M7/30 ,  G06F2212/602

Abstract: A processor that includes compression instructions to compress multiple adjacent data blocks of uncompressed read-only data stored in memory into one compressed read-only data block and store the compressed read-only data block in multiple adjacent blocks in the memory is provided. During execution of an application to operate on the read-only data, one of the multiple adjacent blocks storing the compressed read-only block is read from memory, stored in a prefetch buffer and decompressed in the memory controller. In response to a subsequent request during execution of the application for an adjacent data block in the compressed read-only data block, the uncompressed adjacent block is read directly from the prefetch buffer.