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    Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same
    484.
    发明申请
    Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same 有权
    具有自对准浮动和擦除门的非易失性存储单元及其制造方法

    公开(公告)号：US20140307511A1

    公开(公告)日：2014-10-16

    申请号：US14252929

    申请日：2014-04-15

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Jinho Kim ,  Xian Liu

    IPC: H01L27/115 ,  G11C16/12 ,  G11C16/14 ,  H01L29/66

    CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

    Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region.

    Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，用于控制其导电性。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘，以控制其导电性。 擦除栅极至少部分地布置在浮栅上并与浮栅绝缘。 导电耦合栅极设置在沟槽中，与浮动栅极相邻并与其隔离，并且与源极区域隔离并且绝缘。

    SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES
    485.
    发明申请
    SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES 有权
    非易失性存储器感知的系统和方法，包括选择性/差分阈值电压特性

    公开(公告)号：US20140293724A1

    公开(公告)日：2014-10-02

    申请号：US14229763

    申请日：2014-03-28

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van TRAN ,  Samar SAHA

    IPC: G11C7/06

    CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C16/28 ,  H01L21/28282 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/792

    Abstract: Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.

    Abstract translation: 公开了用于通过使用具有差分阈值电压的MOS晶体管来提供选择性阈值电压特性的系统和方法。 在一个示例性实施例中，提供了一种金属氧化物半导体器件，其包括半导体材料的衬底，其具有源极区，漏极区和它们之间的沟道区，沟道区上方的绝缘层和绝缘层的栅极部。 此外，关于器件，绝缘层的形状和/或接合区域的形状或注入在栅极 - 漏极和栅极 - 源极结之间具有不同的尺寸，以提供不同的阈值电压 他们。

    Non-volatile Memory Cell Having A Trapping Charge Layer In A Trench And An Array And A Method Of Manufacturing Therefor
    487.
    发明申请
    Non-volatile Memory Cell Having A Trapping Charge Layer In A Trench And An Array And A Method Of Manufacturing Therefor 有权
    在沟槽和阵列中具有捕获电荷层的非易失性存储单元及其制造方法

    公开(公告)号：US20140264530A1

    公开(公告)日：2014-09-18

    申请号：US13829111

    申请日：2013-03-14

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do

    IPC: H01L29/792 ,  H01L29/66 ,  H01L27/105

    CPC classification number: H01L29/66833 ,  H01L21/0217 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7926

    Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

    Abstract translation: 通过在衬底表面形成沟槽形成的存储单元。 第一和第二间隔开的区域形成在衬底中，其间具有通道区域。 第一区域形成在沟槽下方。 沟道区域包括沿着沟槽的侧壁延伸的第一部分和沿衬底的表面延伸的第二部分。 沟槽中的电荷捕获层与沟道区的第一部分相邻并与其绝缘，用于控制沟道区第一部分的导通。 沟槽中的导电栅极与电荷俘获层相邻并且与第一区绝缘，并与电荷捕获层电容耦合。 导电控制栅极设置在沟道区域的第二部分上并与沟道区域的第二部分绝缘，用于控制其导通。

    Mixed Voltage Non-volatile Memory Integrated Circuit With Power Saving
    488.
    发明申请
    Mixed Voltage Non-volatile Memory Integrated Circuit With Power Saving 有权
    具有省电的混合电压非易失性存储器集成电路

    公开(公告)号：US20140226409A1

    公开(公告)日：2014-08-14

    申请号：US14257335

    申请日：2014-04-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C16/30

    CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

    Abstract: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. The voltage regulator is enabled by a controller.

    Abstract translation: 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压，并由接收第一电压的电压调节器产生。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 电压调节器由控制器使能。

    Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate
    489.
    发明申请
    Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate 有权
    使用耦合栅极操作分离栅极闪存单元的方法

    公开(公告)号：US20140198578A1

    公开(公告)日：2014-07-17

    申请号：US14216776

    申请日：2014-03-17

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'mani

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

    Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

    Abstract translation: 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域的第一和第二区域，设置在所述沟道区域和所述第一区域上方的浮置栅极，设置在所述沟道区域上并横向邻近所述第二区域的方法 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

    NON-VOLATILE MEMORY SYSTEMS AND METHODS
    490.
    发明申请
    NON-VOLATILE MEMORY SYSTEMS AND METHODS 有权
    非易失性存储器系统和方法

    公开(公告)号：US20140198568A1

    公开(公告)日：2014-07-17

    申请号：US14140452

    申请日：2013-12-24

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Sakhawat M. Khan

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C27/005 ,  G11C2211/5634

    Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

    Abstract translation: 为数字多位非易失性存储器集成系统提供高速电压模式感测。 一个实施例具有本地源跟随器阶段，之后是高速公共源级。 另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。 另一个实施例具有公共源级，之后是源跟随器。 使用自动归零方案。 使用电容感测方案。 描述多级并行操作。

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