公开(公告)号：US20070080452A1

公开(公告)日：2007-04-12

申请号：US11514329

申请日：2006-09-01

Applicant: Chen-Ya- Chi ,  Chun-Ying Lin ,  An-Hong Liu ,  Yi-Chang Lee ,  Hsiang-Ming Huang

Inventor： Chen-Ya- Chi ,  Chun-Ying Lin ,  An-Hong Liu ,  Yi-Chang Lee ,  Hsiang-Ming Huang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10977 ,  H05K2203/049 ,  H05K2203/0597 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A bump structure mainly includes a metal core, a buffer encapsulant, and a metal cap where the metal core is a stud bump formed by wire bonding. The buffer encapsulant encapsulates the metal core. A metal cap is formed on the top surface of the buffer encapsulant and is electrically connected to the metal core. Therefore, the bump structure possesses excellent resistance of thermal stress to reduce or even eliminate metal fatigue in the bump without causing electrical shorts in the package.

Abstract translation: 凸块结构主要包括金属芯，缓冲密封剂和金属盖，其中金属芯是通过引线键合形成的柱形凸块。 缓冲密封剂封装金属芯。 金属盖形成在缓冲密封剂的顶表面上并与金属芯电连接。 因此，凸块结构具有优异的热应力阻力，以减少或甚至消除凸块中的金属疲劳，而不会导致封装中的电短路。

公开(公告)号：US08106494B2

公开(公告)日：2012-01-31

申请号：US13016341

申请日：2011-01-28

Applicant: Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

Inventor： Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

IPC: H01L23/495

CPC classification number: H01L21/4842 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K3/3426 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2201/10787 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract translation: 由无引线封装采用的引线框架包括多个封装单元和胶带。 每个封装单元具有带有多个开口的管芯焊盘和设置在多个开口中的多个销。 粘合带粘附到多个封装单元的表面并固定芯片焊盘和多个引脚。

公开(公告)号：US20110136299A1

公开(公告)日：2011-06-09

申请号：US13016453

申请日：2011-01-28

Applicant: Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

Inventor： Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

IPC: H01L21/60

CPC classification number: H01L21/4842 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K3/3426 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2201/10787 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract translation: 由无引线封装采用的引线框架包括多个封装单元和胶带。 每个封装单元具有带有多个开口的管芯焊盘和设置在多个开口中的多个销。 粘合带粘附到多个封装单元的表面并固定芯片焊盘和多个引脚。

公开(公告)号：US07851896B2

公开(公告)日：2010-12-14

申请号：US12201236

申请日：2008-08-29

Applicant: Geng-Shin Shen ,  Chun-Ying Lin ,  Shih-Wen Chou

Inventor： Geng-Shin Shen ,  Chun-Ying Lin ,  Shih-Wen Chou

IPC: H01L23/495 ,  H01L23/12

CPC classification number: H01L21/6835 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49534 ,  H01L23/49558 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface, wherein a part of the first surface is exposed by the first solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the chip and the bonding wires.

Abstract translation: 提供了包括图案化导电层，第一阻焊层，芯片，多个接合线和模塑料的四平坦非导体（QFN）芯片封装。 图案化导电层具有彼此相对的第一表面和第二表面。 第一阻焊层设置在第一表面上，其中第一表面的一部分被第一阻焊层暴露。 芯片设置在第一阻焊层上，其中第一阻焊层位于图案化导电层和芯片之间。 接合线与第一阻焊层暴露的芯片和图案化的导电层电连接。 模塑料封装图形导电层，第一阻焊层，芯片和接合线。

公开(公告)号：US07803667B2

公开(公告)日：2010-09-28

申请号：US12270679

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/44

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49558 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Chips are bonded onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed and the molding compound and the patterned conductive layer are separated.

Abstract translation: 提供了一种用于四边形扁平无铅（QFN）芯片封装结构的制造工艺。 首先，提供具有凹陷的导电层和导电层上的图案化阻焊层，其中图案化阻焊层覆盖导电层的凹部。 去除由图案化的阻焊层未覆盖的导电层的一部分，以便形成图案化的导电层。 芯片被结合到图案化的导电层上，使得图案化的阻焊层和芯片在图案化导电层的同一侧。 芯片通过接合线电连接到图案化导电层，其中芯片和接合线位于图案化导电层的相同侧。 形成至少一种模塑料，并分离模塑料和图案化的导电层。

公开(公告)号：US07803666B2

公开(公告)日：2010-09-28

申请号：US12270666

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/44

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49558 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer are between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Abstract translation: 提供了一种用于四边形扁平无铅（QFN）芯片封装结构的制造工艺。 首先，提供图案化导电层和图案化导电层上的图案化阻焊层。 多个芯片被结合到图案化的阻焊层上，使得图案化的阻焊层位于芯片和图案化的导电层之间。 芯片通过多根接合线与图案化导电层电连接，其中芯片和接合线位于图案化导电层的同一侧。 形成至少一种模塑料以封装图案化的导电层，图案化的阻焊层，芯片和接合线。 然后，分离模塑料，图案化导电层和图案化阻焊层。

公开(公告)号：US07795079B2

公开(公告)日：2010-09-14

申请号：US12270655

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/44

CPC classification number: H01L21/4857 ,  H01L21/4828 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49558 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer exposed by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated.

Abstract translation: 提供了一种用于四边形扁平无铅（QFN）芯片封装结构的制造工艺。 首先，提供在导电层上具有多个凹部的导电层和图案化阻焊层，其中图案化的阻焊层覆盖导电层的凹部。 多个芯片被结合到图案化的阻焊层上，使得图案化的阻焊层位于芯片和导电层之间。 芯片通过多根接合线与导电层电连接。 形成至少一种模塑料以封装导电层，图案化阻焊层，芯片和接合线。 去除由图案化的阻焊层暴露的导电层的一部分，以便形成图案化的导电层。 然后，分离模塑料和图案化导电层。

公开(公告)号：US07696629B2

公开(公告)日：2010-04-13

申请号：US11872205

申请日：2007-10-15

Applicant: Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

Inventor： Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/4918 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

Abstract translation: 提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。 设置在电介质层上的图案化电路层通过接合线电连接到基板。 设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。

公开(公告)号：US20090321918A1

公开(公告)日：2009-12-31

申请号：US12506255

申请日：2009-07-21

Applicant: Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

Inventor： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

IPC: H01L23/498

CPC classification number: H01L21/563 ,  H01L23/3135 ,  H01L24/97 ,  H01L33/642 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

Abstract translation: 芯片封装包括热增强板，围绕热增强板接触并与热增强板电绝缘，设置在触点和热增强板上的膜状电路层，导电粘合剂层，第一模制件和 设置在膜状电路层上的至少一个芯片。 导电性粘合剂层设置在触点和通过导电粘合剂层与触点电连接的膜状电路层之间。 芯片具有背面，有源表面和设置在其上的许多凸块，并且芯片经由凸块电连接到膜状电路层。 第一模制品至少封装热增强板的一部分，导电粘合剂层，触点的一部分和膜状电路层的至少一部分。 因此，提高了发光芯片封装的散热效率。

公开(公告)号：US20090127684A1

公开(公告)日：2009-05-21

申请号：US12262580

申请日：2008-10-31

Applicant: HENG CHANG KUO ,  PO KAI HOU ,  CHUN YING LIN

Inventor： HENG CHANG KUO ,  PO KAI HOU ,  CHUN YING LIN

IPC: H01L23/495

CPC classification number: H01L23/49541 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49565 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, an insulating layer, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of slots are disposed around each of the package units. The insulating layer is filled in a plurality of slots between the package areas. The tape (film) fixes the plurality of package areas, the plurality of connection portions, the plurality of die pads, and the plurality of leads in place.

Abstract translation: 用于无引线封装的引线框架包括多个封装区域，多个槽，绝缘层和带（膜）。 每个封装区域包括多个封装单元，每个封装单元包括管芯焊盘和围绕管芯焊盘的多个引线。 多个狭槽围绕每个包装单元设置。 绝缘层填充在封装区域之间的多个槽中。 带（膜）将多个封装区域，多个连接部分，多个管芯焊盘和多个引线固定就位。