公开(公告)号：US06667207B2

公开(公告)日：2003-12-23

申请号：US10246110

申请日：2002-09-18

Applicant: Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Douglas D. Coolbaugh ,  Evgeni P. Gousev ,  Harald F. Okorn-Schmidt

Inventor： Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Douglas D. Coolbaugh ,  Evgeni P. Gousev ,  Harald F. Okorn-Schmidt

IPC: H01L218249

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/60 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/94

Abstract: Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

Abstract translation: 提供了形成前端的方法（FEOL）电容器，例如多晶硅 - 多晶硅电容器和金属 - 绝缘体 - 硅电容器，其能够将高介电常数（k大于约8）并入电容器 结构体。 本发明的方法提供了用于高频响应的顶部和底部电极具有低串联电阻的高电容/面积器件。 本发明的方法提供了芯片尺寸的显着降低，特别是在使用大面积电容的模拟和混合信号应用中。

公开(公告)号：US06656815B2

公开(公告)日：2003-12-02

申请号：US09826054

申请日：2001-04-04

Applicant: Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  John C. Malinowski

Inventor： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  John C. Malinowski

IPC: H01L2176

CPC classification number: G03F9/708 ,  G03F9/7084 ,  H01L21/8249 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a BiCMOS device having a deep subcollector region and self-aligned alignment marks is provided. The inventive method includes the steps of: (a) lithographically forming a first patterned layer comprising a thick dielectric material on a surface of a material stack formed on a semiconductor substrate, the first patterned layer including at least one opening therein and the semiconductor substrate having at least an alignment area; (b) performing a high-energy/high-dose implant through the at least one opening and the material stack so as to form at least one deep subcollector region in the semiconductor substrate; (c) lithographically forming a second patterned layer (photoresist or dielectric) predominately outside the first patterned layer in the alignment area; and (d) etching through the material stack to form alignment marks in the underlying semiconductor substrate using the first patterned layer as an alignment mark mask.

公开(公告)号：US20110127635A1

公开(公告)日：2011-06-02

申请号：US13023579

申请日：2011-02-09

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC: H01L23/58

CPC classification number: H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Abstract translation: 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

公开(公告)号：US20110108919A1

公开(公告)日：2011-05-12

申请号：US13006001

申请日：2011-01-13

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  John E. Florkey ,  Heidi L. Greer ,  Robert M. Rassel ,  Anthony K. Stamper ,  Kunal Vaed

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  John E. Florkey ,  Heidi L. Greer ,  Robert M. Rassel ,  Anthony K. Stamper ,  Kunal Vaed

IPC: H01L27/12

CPC classification number: H01L29/8605 ,  H01L27/0802 ,  H01L28/20

Abstract: The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

Abstract translation: 本发明提供一种包括具有改进控制的掩埋电阻器的半导体结构，其中电阻器制造在半导体衬底的也存在于衬底中的阱区域下方的区域中。 根据本发明，本发明的结构包括至少含有一个阱区的半导体衬底; 以及位于半导体衬底的位于所述阱区之下的区域中的掩埋电阻器。 本发明还提供一种制造这样的结构的方法，其中使用深离子注入工艺来形成掩埋电阻器，并且在形成阱区域中使用较浅的离子注入工艺。

公开(公告)号：US20100297825A1

公开(公告)日：2010-11-25

申请号：US12849086

申请日：2010-08-03

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Jonghae Kim ,  Jean-Olivier Plouchart ,  Anthony K. Stamper

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Jonghae Kim ,  Jean-Olivier Plouchart ,  Anthony K. Stamper

IPC: H01L21/02

CPC classification number: H01L23/5228 ,  H01L23/5227 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.

Abstract translation: 通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。 电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。 电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

公开(公告)号：US07829452B2

公开(公告)日：2010-11-09

申请号：US12348934

申请日：2009-01-06

Applicant: Douglas D. Coolbaugh ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552

Abstract: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

Abstract translation: 端子焊盘和制造端子焊盘的方法。 所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。 所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

公开(公告)号：US20100117237A1

公开(公告)日：2010-05-13

申请号：US12269069

申请日：2008-11-12

Applicant: Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

Inventor： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

IPC: H01L23/52 ,  H01L21/02

CPC classification number: H01L21/743 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

Abstract translation: 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

公开(公告)号：US07691717B2

公开(公告)日：2010-04-06

申请号：US11458494

申请日：2006-07-19

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

IPC: H01L21/20

CPC classification number: H01L27/0802 ,  H01L21/26513 ,  H01L28/20

Abstract: A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

Abstract translation: 含多晶硅的电阻器包括：（1）选自硼和二氟化硼的p掺杂剂; 和（2）选自砷和磷的n掺杂剂。 p掺杂剂和n掺杂剂中的每一个掺杂剂的掺杂剂浓度从每立方厘米约1e18至约1e21掺杂剂原子。 用于形成多晶硅电阻器的方法使用相对于每平方厘米约1e14至约1e16掺杂剂离子的注入剂量。 p掺杂剂和n掺杂剂可以同时或顺序地提供。 对于具有约100至约5000欧姆/平方的薄层电阻的多晶硅电阻器，该方法提供某些多晶硅电阻器的薄层电阻百分比标准偏差小于约1.5％。

公开(公告)号：US07645675B2

公开(公告)日：2010-01-12

申请号：US11275544

申请日：2006-01-13

Applicant: Douglas D. Coolbaugh ,  Hanyi Ding ,  Ebenezer E. Eshun ,  Michael D. Gordon ,  Zhong-Xiang He ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Hanyi Ding ,  Ebenezer E. Eshun ,  Michael D. Gordon ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H01L21/20

CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

Abstract translation: 形成在集成电路的后端的平行电容器采用与后端（具有相同材料，厚度等）的该级别上的其它互连件同时形成的导电电容器板。 使用与后端（优选双镶嵌）级别上的其它互连件相同的工艺将电容器板设置在层间电介质中。 一些版本的电容器在板中具有穿孔，并且垂直导电构件连接相同极性的所有板，从而与实心板相比增加了可靠性，节省了空间并增加了电容密度。

公开(公告)号：US20090253239A1

公开(公告)日：2009-10-08

申请号：US12062262

申请日：2008-04-03

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Kimball M. Watson

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Kimball M. Watson

IPC: H01L21/331

CPC classification number: H01L29/41708 ,  H01L27/0629 ,  H01L27/0658 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/78

Abstract: A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.

Abstract translation: 一种用于制造低电阻电阻器的方法，例如用于双极结型晶体管的镇流电阻器。 可以使用适当的薄层电阻的层来制造电阻器，以便在紧凑的布局中实现低电阻值。 该方法可以依赖于传统CMOS工艺流程已经提供的层，例如接触插塞和完全硅化（FUSI）金属栅极。