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    Multi-level nonvolatile memory devices using variable resistive elements
    42.
    发明授权
    Multi-level nonvolatile memory devices using variable resistive elements 有权
    使用可变电阻元件的多级非易失性存储器件

    公开(公告)号：US08358527B2

    公开(公告)日：2013-01-22

    申请号：US12656754

    申请日：2010-02-16

    Applicant: In-Gyu Baek ,  Hyun-Jun Sim ,  Hong-Sik Yoon ,  Jin-Shi Zhao ,  Min-Young Park

    Inventor： In-Gyu Baek ,  Hyun-Jun Sim ,  Hong-Sik Yoon ,  Jin-Shi Zhao ,  Min-Young Park

    IPC: G11C11/00 ,  H01L47/00

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2211/5641 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72

    Abstract: Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto.

    Abstract translation: 使用可变电阻元件的多级非易失性存储器件，多级非易失性存储器件包括字线，位线和耦合在字线和位线之间的多电平存储器单元，多电平存储器单元 当施加具有相同极性的第一和第二写入偏置时，具有高于第一电阻电平的第一电阻电平和第二电阻电平，以及在第一和第二电阻电平之间范围内的第三电阻电平和第四电阻电平，当 施加具有彼此不同极性的第三和第四写入偏置。

    NON-VOLATILE MEMORY DEVICE HAVING VARIABLE RESISTANCE ELEMENT AND METHOD OF FABRICATING THE SAME
    43.
    发明申请
    NON-VOLATILE MEMORY DEVICE HAVING VARIABLE RESISTANCE ELEMENT AND METHOD OF FABRICATING THE SAME 有权
    具有可变电阻元件的非易失性存储器件及其制造方法

    公开(公告)号：US20130009122A1

    公开(公告)日：2013-01-10

    申请号：US13462844

    申请日：2012-05-03

    Applicant: CHAN-JIN PARK ,  HYUN-SU JU ,  IN-GYU BAEK

    Inventor： CHAN-JIN PARK ,  HYUN-SU JU ,  IN-GYU BAEK

    IPC: H01L47/00

    CPC classification number: H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.

    Abstract translation: 非易失性存储器件包括下成型层，下成型层上的水平互连线，水平互连线上的上成型层，垂直穿过上成型层，水平互连线和下成型件的柱 层和介于柱和成型层之间的缓冲层。 该装置还包括可变电阻材料和插在支柱和水平互连线之间的二极管层。

    BIDIRECTIONAL RESISTIVE MEMORY DEVICES USING SELECTIVE READ VOLTAGE POLARITY
    44.
    发明申请
    BIDIRECTIONAL RESISTIVE MEMORY DEVICES USING SELECTIVE READ VOLTAGE POLARITY 失效
    使用选择性读取电压极性的双向电阻存储器件

    公开(公告)号：US20120182786A1

    公开(公告)日：2012-07-19

    申请号：US13349167

    申请日：2012-01-12

    Applicant: In-Gyu Baek ,  Hyung-Rok Oh ,  Hong-Sun Hwang

    Inventor： In-Gyu Baek ,  Hyung-Rok Oh ,  Hong-Sun Hwang

    IPC: G11C11/21

    CPC classification number: G11C13/004 ,  G11C8/10 ,  G11C11/16 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007

    Abstract: A memory device includes a memory cell array including a plurality of memory cells, each including a bidirectional variable resistance element and an input/output circuit configured to determine a polarity for a read voltage to be applied to a selected memory cell among the plurality of memory cells and to apply the read voltage with the determined polarity to the selected memory cell. The input/output circuit may include a polarity determination circuit configured to determine the polarity responsive to a determination mode signal and a driver circuit configured to apply the read voltage with the determined polarity to the selected memory cell.

    Abstract translation: 存储器件包括存储单元阵列，其包括多个存储器单元，每个存储器单元包括双向可变电阻元件和输入/输出电路，该输入/输出电路被配置为确定要施加到多个存储器中的选定存储单元的读取电压的极性 并将所确定的极性的读取电压施加到所选存储单元。 输入/输出电路可以包括极性确定电路，其被配置为响应于确定模式信号确定极性，并且驱动器电路被配置为将所确定的极性的读取电压施加到所选存储单元。

    SEMICONDUCTOR MEMORY DEVICE HAVING STACKED STRUCTURE INCLUDING RESISTOR-SWITCHED BASED LOGIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME
    45.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING STACKED STRUCTURE INCLUDING RESISTOR-SWITCHED BASED LOGIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME 有权
    具有堆叠结构的半导体存储器件，包括基于电阻开关的逻辑电路及其制造方法

    公开(公告)号：US20120063194A1

    公开(公告)日：2012-03-15

    申请号：US13224410

    申请日：2011-09-02

    Applicant: In-gyu BAEK ,  Hong-sun HWANG ,  Hak-soo YU ,  Chul-woo PARK

    Inventor： In-gyu BAEK ,  Hong-sun HWANG ,  Hak-soo YU ,  Chul-woo PARK

    IPC: G11C11/00 ,  H01L45/00

    CPC classification number: H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

    Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

    Abstract translation: 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

    Methods of fabricating non-volatile memory devices with discrete resistive memory material regions
    47.
    发明申请
    Methods of fabricating non-volatile memory devices with discrete resistive memory material regions 审中-公开
    使用分立电阻记忆材料区域制造非易失性存储器件的方法

    公开(公告)号：US20110081762A1

    公开(公告)日：2011-04-07

    申请号：US12880721

    申请日：2010-09-13

    Applicant: Suk-hun Choi ,  In-gyu Baek ,  Jun-young Lee ,  Jung-hyeon Kim ,  Chang-ki Hong ,  Yoon-ho Son

    Inventor： Suk-hun Choi ,  In-gyu Baek ,  Jun-young Lee ,  Jung-hyeon Kim ,  Chang-ki Hong ,  Yoon-ho Son

    IPC: H01L21/02

    CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L28/20 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

    Abstract: A semiconductor memory device includes a first conductive line on a semiconductor substrate, an interlayer insulating layer on the first conductive line, a second conductive line on the interlayer insulating layer, and a memory cell in an hole through the interlayer insulating layer wherein the first and second conductive lines cross, the memory cell including a discrete resistive memory material region disposed in the hole and electrically connected between the first and second conductive lines. The resistive memory material region may be substantially contained within the hole. In some embodiments, contact between the resistive memory material region and the interlayer insulating layer is substantially limited to sidewalls of the interlayer insulating layer in the hole.

    Abstract translation: 半导体存储器件包括半导体衬底上的第一导电线，第一导线上的层间绝缘层，层间绝缘层上的第二导线，以及穿过层间绝缘层的孔中的存储单元，其中， 第二导线交叉，存储单元包括设置在孔中并电连接在第一和第二导线之间的分立的电阻性存储器材料区域。 电阻性存储器材料区域可以基本上包含在孔内。 在一些实施例中，电阻性存储器材料区域和层间绝缘层之间的接触基本上限于孔中的层间绝缘层的侧壁。

    RESISTIVE MEMORY CELLS AND DEVICES HAVING ASYMMETRICAL CONTACTS
    48.
    发明申请
    RESISTIVE MEMORY CELLS AND DEVICES HAVING ASYMMETRICAL CONTACTS 有权
    电阻记忆体和具有不对称接触的装置

    公开(公告)号：US20100044666A1

    公开(公告)日：2010-02-25

    申请号：US12612187

    申请日：2009-11-04

    Applicant: In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

    Inventor： In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

    IPC: H01L47/00

    CPC classification number: H01L45/04 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    Abstract: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

    Abstract translation: 存储单元包括衬底中的插塞式第一电极，设置在第一电极上的磁阻存储元件，以及设置在与第一电极相对的磁阻存储元件上的第二电极。 第二电极具有与磁阻存储元件重叠的区域，其大于第一电极和磁阻存储元件的重叠区域。 例如，第一表面可以是基本上圆形的并且具有小于第二表面的最小平面尺寸（例如，宽度）的直径。 磁阻存储元件可以包括巨磁阻材料，例如具有钙钛矿相和/或过渡金属氧化物的绝缘材料。

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