公开(公告)号：US09052724B2

公开(公告)日：2015-06-09

申请号：US13568248

申请日：2012-08-07

Applicant: Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie

Inventor： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie

IPC: H01L23/34 ,  G05D23/00 ,  G05D23/19 ,  H01L23/38 ,  H01L23/473 ,  H05K7/20 ,  G06F1/20

CPC classification number: G05D23/1919 ,  G06F1/206 ,  H01L23/38 ,  H01L23/473 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K7/20272 ,  H05K7/20281 ,  H05K7/20518 ,  H01L2924/00

Abstract: An integrated circuit chip having micro-channels formed in multiple regions of the integrated circuit chip and a method of cooling the integrated circuit chip. The method includes for any region of the multiple regions, allowing a coolant to flow through micro-channels of the region only when a temperature of the region exceed a first specified temperature and blocking the coolant from flowing through the micro-channels of the region when a temperature of the region is below a second specified temperature.

Abstract translation: 具有形成在集成电路芯片的多个区域中的微通道的集成电路芯片和冷却集成电路芯片的方法。 该方法包括对于多个区域的任何区域，只有当该区域的温度超过第一规定温度并且阻止冷却剂流过该区域的微通道时，冷却剂才能流过该区域的微通道， 该区域的温度低于第二规定温度。

公开(公告)号：US08853007B2

公开(公告)日：2014-10-07

申请号：US13024994

申请日：2011-02-10

Applicant: Kerry Bernstein ,  Sri M. Sri-Jayantha

Inventor： Kerry Bernstein ,  Sri M. Sri-Jayantha

IPC: H01L23/36 ,  H01L23/373 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/3672 ,  H01L23/3738 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/19041 ,  H01L2924/01014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of dissipating heat from a heat source includes providing a plurality of heat flux paths in a plane of the heat source to remove heat from the heat source.

Abstract translation: 从热源散热的方法包括在热源的平面中提供多个热通路，以从热源移除热量。

公开(公告)号：US20130249596A1

公开(公告)日：2013-09-26

申请号：US13426776

申请日：2012-03-22

Applicant: Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, JR. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

Inventor： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, JR. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

IPC: H03K19/00

CPC classification number: H03K19/0966 ,  H03K19/0013

Abstract: Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

Abstract translation: 电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。 当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。 本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中 只有在本地逻辑设备中已经满足设置时间之后）。 这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

公开(公告)号：US08441042B2

公开(公告)日：2013-05-14

申请号：US12561827

申请日：2009-09-17

Applicant: Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

Inventor： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

IPC: H01L21/76

CPC classification number: H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract translation: 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

公开(公告)号：US08421126B2

公开(公告)日：2013-04-16

申请号：US13164173

申请日：2011-06-20

Applicant: Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

Inventor： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC: H01L27/085

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures. The semiconductor structures include two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers or bonding them back to back utilizing an inter-substrate dielectric layer and a bonding layer between the buried oxide layers. The structures include contacts formed in the upper wafer to devices in the lower wafer and wiring levels formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract translation: 半导体结构。 半导体结构包括两个绝缘体上硅晶片，其中制造了器件，并且利用掩埋氧化物层将它们背靠背接合，或者使用衬底间介质层和掩埋氧化物层之间的结合层将它们背靠背连接。 这些结构包括形成在上晶片中的触点与下晶片中的器件和形成在上晶片上的布线电平。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US08417503B2

公开(公告)日：2013-04-09

申请号：US10023235

申请日：2001-12-17

Applicant: Kerry Bernstein ,  Josef S. Watts ,  Richard Q. Williams

Inventor： Kerry Bernstein ,  Josef S. Watts ,  Richard Q. Williams

IPC: G06F17/50 ,  G06F9/455 ,  G06F11/30 ,  G06F19/00

CPC classification number: G06F17/5036 ,  G06F17/5022

Abstract: A method and structure for a computer model of a device has a performance parameter. The performance parameter includes a first bounded range and a second bounded range. The first bounded range has performance parameter variations within a single manufacturing process, and the second bounded range has performance parameter variations of different device designs.

公开(公告)号：US20120305929A1

公开(公告)日：2012-12-06

申请号：US13572742

申请日：2012-08-13

Applicant: Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

Inventor： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

IPC: H01L29/786

CPC classification number: H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract translation: 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

公开(公告)号：US08298906B2

公开(公告)日：2012-10-30

申请号：US12511545

申请日：2009-07-29

Applicant: Kerry Bernstein ,  Francis Roger White

Inventor： Kerry Bernstein ,  Francis Roger White

IPC: H01L21/20

CPC classification number: H01L21/3065 ,  H01L21/76898 ,  H01L29/66181

Abstract: A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag.

Abstract translation: 使用通过硅通孔（TSV）蚀刻的RIE滞后来形成沟槽去耦电容器。 一种方法包括在单个RIE工艺中蚀刻晶片中的通孔沟槽和电容器沟槽。 通孔沟槽具有第一深度，并且由于RIE滞后，电容器沟槽具有小于第一深度的第二深度。

公开(公告)号：US20120262197A1

公开(公告)日：2012-10-18

申请号：US13533191

申请日：2012-06-26

Applicant: Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

Inventor： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

IPC: G01R31/3187 ,  G01R1/067 ,  G01R31/00 ,  G01R31/02

CPC classification number: H01L22/32 ,  H01L21/4846 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2224/13005 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

公开(公告)号：US08133772B2

公开(公告)日：2012-03-13

申请号：US13075271

申请日：2011-03-30

Applicant: John E. Barth, Jr. ,  Kerry Bernstein ,  Ethan H. Cannon ,  Francis R. White

Inventor： John E. Barth, Jr. ,  Kerry Bernstein ,  Ethan H. Cannon ,  Francis R. White

IPC: H01L21/8242

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/66181

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

Abstract translation: 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。