中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.015 seconds)

    Modified gate processing for optimized definition of array and logic devices on same chip
    42.
    发明授权
    Modified gate processing for optimized definition of array and logic devices on same chip 失效
    改进的门处理，用于在同一芯片上优化阵列和逻辑器件的定义

    公开(公告)号：US06403423B1

    公开(公告)日：2002-06-11

    申请号：US09713272

    申请日：2000-11-15

    Applicant: Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

    Inventor： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

    IPC: H01L21336

    CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

    Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

    Abstract translation: 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些电介质间隔物允许阵列栅极导体抗蚀剂线被制成 - 小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

    Integrated circuits having reduced stress in metallization
    43.
    发明授权
    Integrated circuits having reduced stress in metallization 失效
    集成电路在金属化中具有降低的应力

    公开(公告)号：US06208008B1

    公开(公告)日：2001-03-27

    申请号：US09260702

    申请日：1999-03-02

    Applicant: Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    Inventor： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    IPC: H01L2941

    CPC classification number: H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    Abstract: The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

    Abstract translation: 通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常引起的应力可以通过将与形成为集成电路的一部分的特征相关联的下角 在施加外部（即钝化）层之前，例如，互连）。 关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化 或者沿着垂直侧壁的下部产生锥形间隔物。 这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。 对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

    Multilayer sidewall spacer for seam protection of a patterned structure
    46.
    发明授权
    Multilayer sidewall spacer for seam protection of a patterned structure 有权
    用于图案结构的接缝保护的多层侧壁间隔件

    公开(公告)号：US08673725B2

    公开(公告)日：2014-03-18

    申请号：US12751926

    申请日：2010-03-31

    Applicant: David L. O'Meara ,  Anthony Dip ,  Aelan Mosden ,  Pao-Hwa Chou ,  Richard A Conti

    Inventor： David L. O'Meara ,  Anthony Dip ,  Aelan Mosden ,  Pao-Hwa Chou ,  Richard A Conti

    IPC: H01L29/78

    CPC classification number: H01L21/28247 ,  H01L29/6656

    Abstract: A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.

    Abstract translation: 描述了具有多层侧壁间隔件和形成方法的半导体器件。 在一个实施例中，该方法包括在衬底的表面上提供含有图案化结构的衬底，并且在第一衬底温度下在第一衬底温度下沉积在图案化结构上的第一间隔层，其中第一间隔层包含第一材料。 该方法还包括在不同于第一衬底温度的第二衬底温度下在图案化衬底上沉积第二间隔层，其中第一和第二材料含有相同的化学元素，并且沉积步骤以任何顺序进行。 然后蚀刻第一和第二间隔层以在图案化结构上形成多层侧壁间隔物。

    Mask forming and implanting methods using implant stopping layer
    47.
    发明授权
    Mask forming and implanting methods using implant stopping layer 有权
    使用植入物停止层的掩模形成和植入方法

    公开(公告)号：US07998871B2

    公开(公告)日：2011-08-16

    申请号：US12145915

    申请日：2008-06-25

    Applicant: Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

    Inventor： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

    IPC: H01L21/302

    CPC classification number: H01L21/266 ,  H01L21/26513 ,  Y10T428/24992

    Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.

    Abstract translation: 形成用于植入衬底的掩模和使用具有光刻胶的注入阻挡层进行植入的方法提供了较低的纵横比掩模，其在去除掩模期间对衬底中的沟槽隔离造成最小的损害。 在一个实施例中，形成掩模的方法包括：在衬底上沉积注入阻挡层; 在所述注入阻挡层上沉积光致抗蚀剂，所述注入阻挡层的密度大于所述光致抗蚀剂; 通过去除光致抗蚀剂的一部分以暴露植入物停止层，在光致抗蚀剂中形成图案; 并通过蚀刻将图案转移到植入物停止层中以形成掩模。 注入停止层可以包括：氢化碳化锗，氮化碳化锗，氟化锗碳化物和/或无定形锗碳氢化物（GeHX），其中X包括碳。 方法/掩模减少了植入过程中的散射，因为掩模具有比常规掩模更高的密度。

    Method of forming nitride films with high compressive stress for improved PFET device performance
    48.
    发明授权
    Method of forming nitride films with high compressive stress for improved PFET device performance 有权
    形成具有高压缩应力的氮化物薄膜以提高PFET器件性能的方法

    公开(公告)号：US07804136B2

    公开(公告)日：2010-09-28

    申请号：US11875217

    申请日：2007-10-19

    Applicant: Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

    Inventor： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

    IPC: H01L23/62

    CPC classification number: H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

    Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

    Abstract translation: 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

    Method for forming damascene structure utilizing planarizing material coupled with compressive diffusion barrier material
    49.
    发明授权
    Method for forming damascene structure utilizing planarizing material coupled with compressive diffusion barrier material 有权
    使用与压缩扩散阻挡材料耦合的平面化材料形成镶嵌结构的方法

    公开(公告)号：US07326651B2

    公开(公告)日：2008-02-05

    申请号：US10905068

    申请日：2004-12-14

    Applicant: Heidi Baks ,  Richard A. Bruff ,  Richard A. Conti ,  Allan Upham

    Inventor： Heidi Baks ,  Richard A. Bruff ,  Richard A. Conti ,  Allan Upham

    IPC: H01L21/302

    CPC classification number: H01L21/76808 ,  H01L21/31144 ,  H01L21/76804

    Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

    Abstract translation: 本发明涉及集成电路器件中的双镶嵌互连结构的制造。 具体地，公开了一种利用平面化材料和压缩扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。 阻挡材料优选具有大于300MPa的压缩应力。 在该方法的优选双镶嵌实施例中，首先在电介质材料中形成通孔，然后将平坦化材料沉积在通孔和介电材料上，并且阻挡材料沉积在平坦化材料上。 然后在成像材料中光刻地形成沟槽，通过阻挡材料蚀刻成平坦化材料，并将沟槽图案转移到电介质材料。 在这些蚀刻步骤期间和之后，去除成像，阻挡层和平坦化材料。 然后可以将所得的双镶嵌结构金属化。 通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

    MASK FORMING AND IMPLANTING METHODS USING IMPLANT STOPPING LAYER AND MASK SO FORMED
    50.
    发明申请
    MASK FORMING AND IMPLANTING METHODS USING IMPLANT STOPPING LAYER AND MASK SO FORMED 失效
    使用植入物层和掩模形成的掩模形成和植入方法

    公开(公告)号：US20070275563A1

    公开(公告)日：2007-11-29

    申请号：US11420321

    申请日：2006-05-25

    Applicant: Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

    Inventor： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/266 ,  H01L21/26513 ,  Y10T428/24992

    Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.

    Abstract translation: 形成用于植入衬底的掩模和使用具有光刻胶的注入阻挡层进行植入的方法提供了较低的纵横比掩模，其在去除掩模期间对衬底中的沟槽隔离造成最小的损害。 在一个实施例中，形成掩模的方法包括：在衬底上沉积注入阻挡层; 在所述注入阻挡层上沉积光致抗蚀剂，所述注入阻挡层的密度大于所述光致抗蚀剂; 通过去除光致抗蚀剂的一部分以暴露植入物停止层，在光致抗蚀剂中形成图案; 并通过蚀刻将图案转移到植入物停止层中以形成掩模。 注入停止层可以包括：氢化碳化锗，氮化碳化锗，氟化锗碳化物和/或无定形锗碳氢化物（GeHX），其中X包括碳。 方法/掩模减少了植入过程中的散射，因为掩模具有比常规掩模更高的密度。

Patent Agency Ranking