公开(公告)号：US20060002196A1

公开(公告)日：2006-01-05

申请号：US11173735

申请日：2005-07-01

申请人： Takaaki Furuyama ,  Satoru Kawamoto

发明人： Takaaki Furuyama ,  Satoru Kawamoto

IPC分类号： G11C7/10

CPC分类号： G11C29/14 ,  G11C29/02

摘要： A memory system (1A) includes a memory section (2A) and a memory control section (3A). The memory section (2A) includes a test circuit (4A), a data register (5A), a data output section (6A), and a memory core section (9A). Data DI is held in the data resistor (5A). The test circuit (4A) outputs write inhibit signal WINH to the memory core section (9A) in response to test signal TEST. Write instruction recognition signal WR which recognizes that a write command is inputted into the memory section (2A) and select signal S are inverted and, in response thereto, retained data DR of the data register (5A) is outputted as output data DO from the data output section (6A). Thus, it is possible to test whether generation, propagation, or recognition operation of a write command CMD and the data DI is normal or not without executing the operation of writing data into a memory cell of the memory section.

摘要翻译： 存储器系统（1A）包括存储器部分（2A）和存储器控制部分（3A）。 存储部分（2A）包括测试电路（4A），数据寄存器（5A），数据输出部分（6A）和存储器核心部分（9A）。 数据DI保存在数据电阻（5A）中。 测试电路（4A）响应于测试信号TEST将写入禁止信号WINH输出到存储器芯部分（9A）。 识别写入指令被输入到存储部分（2A）和选择信号S的写指令识别信号WR被反转，并且作为响应，数据寄存器（5A）的保留数据DR被输出作为输出数据DO 从数据输出部分（6A）。 因此，可以测试写命令CMD和数据DI的生成，传播或识别操作是否正常，而不执行将数据写入存储器部分的存储单元的操作。

公开(公告)号：US20050157574A1

公开(公告)日：2005-07-21

申请号：US11058302

申请日：2005-02-16

申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C7/00 ,  G11C11/4076 ,  G11C11/4094

CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

摘要翻译： 本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化 相等的时间，从而能够防止读出放大器内的短路。

公开(公告)号：US06879200B2

公开(公告)日：2005-04-12

申请号：US09921561

申请日：2001-08-06

申请人： Kazufumi Komura ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Satoru Kawamoto

IPC分类号： G11C8/00 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/14 ,  H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00065

摘要： A delay circuit including a delay section having two or more predetermined delay stages is disclosed. Each predetermined delay stage adds a predetermined delay time to an input signal. The delay circuit also includes selecting switch sections. At least one of the selecting switch sections includes: a buffer section for receiving a delayed input signal from one of the delay stages and a selecting section means directly connected to the buffer section for activating the buffer section to establish a delay path, wherein an output signal from the delay path has a desired delay time.

摘要翻译： 公开了一种包括具有两个或多个预定延迟级的延迟部分的延迟电路。 每个预定延迟级向输入信号添加预定的延迟时间。 延迟电路还包括选择开关部分。 所述选择开关部分中的至少一个包括：用于从所述延迟级之一接收延迟的输入信号的缓冲器部分和直接连接到所述缓冲器部分的用于激活所述缓冲器部分以建立延迟路径的选择部分装置，其中输出 来自延迟路径的信号具有期望的延迟时间。

公开(公告)号：US06847540B2

公开(公告)日：2005-01-25

申请号：US10404153

申请日：2003-04-02

申请人： Yoshiharu Kato ,  Satoru Kawamoto

发明人： Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C11/404 ,  G11C7/14 ,  G11C7/22 ,  G11C11/34 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C7/227 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099

摘要： A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal φCPR. The signal φCPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.

摘要翻译： 即使当器件状态从电源电容器的所有电荷存储节点中的没有存储电荷的状态改变到接通操作状态时，单元板电位也不波动的半导体存储器件包括NMOS晶体管M1 到Mk，用于将来自参考电压生成电路的参考电压VPR的线路VPR作为用于参考电压VCP的馈线（用于参考电压VCP的馈线）的每个单元块B1至Bk中的参考电压产生电路连接。 NMOS晶体管M1至Mk的栅极端子连接到公共信号phiCPR。 信号phiCPR在上电之后的预定时间输出正逻辑电平。 通过在每个单元块B1至Bk中设置用于使线VPR与线VCP短路的NMOS晶体管M1至Mk，在每个单元块B1至Bk中两条线都短路。

公开(公告)号：US06839293B2

公开(公告)日：2005-01-04

申请号：US10288461

申请日：2002-11-06

申请人： Satoru Kawamoto ,  Motoki Mizutani ,  Shinji Nagai ,  Yoshiharu Kato

发明人： Satoru Kawamoto ,  Motoki Mizutani ,  Shinji Nagai ,  Yoshiharu Kato

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C11/401 ,  G11C29/02 ,  G11C29/04 ,  G11C29/06 ,  G11C29/50 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/025 ,  G11C17/14 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/0403

摘要： A semiconductor memory device having a burn-in test capability. The semiconductor memory device includes a detection circuit, which is connected to the plurality of word lines. The detection circuit detects whether a stress voltage for a burn-in test has been applied to all of the word lines along their entire lengths in the burn-in test.

摘要翻译： 具有老化测试能力的半导体存储器件。 半导体存储器件包括连接到多个字线的检测电路。 检测电路检测在老化测试中，老化测试的应力电压是否已沿其整个长度应用于所有字线。

公开(公告)号：US06782522B2

公开(公告)日：2004-08-24

申请号：US10291419

申请日：2002-11-12

申请人： Taku Iida ,  Satoru Kawamoto ,  Toshiaki Yagura

发明人： Taku Iida ,  Satoru Kawamoto ,  Toshiaki Yagura

IPC分类号： G06F1750

CPC分类号： H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01068 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/09727 ,  H05K2201/10734

摘要： A semiconductor electronic part, having a lot of bumps allocated in a checkered pattern, is solder-mounted on a multilayer circuit board. In the multilayer circuit board, a first wiring pattern linked with a first land is finer than a second wiring pattern linked with a second land. Only one first wiring pattern is passable between lands. The second lands are allocated in the outmost line on the uppermost layer of the multilayer circuit board. In the semiconductor electronic part, bumps connectable with the second lands are allocated in the outermost line.

摘要翻译： 具有以方格图案分配的大量凸块的半导体电子部件被焊接安装在多层电路板上。 在多层电路板中，与第一焊盘连接的第一布线图案比与第二焊盘连接的第二布线图案更细。 在陆地之间只能有一个第一个布线图案可以通过。 第二焊盘被分配在多层电路板的最上层的最外层。 在半导体电子部件中，与第二焊盘连接的凸块分配在最外面的线路中。

公开(公告)号：US06658609B1

公开(公告)日：2003-12-02

申请号：US09441803

申请日：1999-11-17

申请人： Syuichi Saito ,  Satoru Kawamoto

发明人： Syuichi Saito ,  Satoru Kawamoto

IPC分类号： G11C2900

CPC分类号： G11C29/34 ,  G11C8/08 ,  G11C2029/1202 ,  G11C2029/1802 ,  G11C2029/2602

摘要： A semiconductor memory device includes a memory cell array having memory cells located at the intersections of bit lines and word lines. Driver circuits are connected to groups of the word lines. A first decoder circuit is connected to the driver circuits to selectively activate them. A second decoder circuit is also connected to the driver circuits to activate selected ones of the word lines. In response to a test signal, the first decoder circuit simultaneously activates all of the driver circuits and the second decoder circuit activates the selected ones of the word lines.

摘要翻译： 半导体存储器件包括具有存储单元的存储单元阵列，位于位线和字线的交点处。 驱动电路连接到字线组。 第一解码器电路连接到驱动器电路以选择性地激活它们。 第二解码器电路也连接到驱动器电路以激活所选择的字线。 响应于测试信号，第一解码器电路同时激活所有的驱动电路，第二解码器电路激活所选择的字线。

公开(公告)号：US06567298B2

公开(公告)日：2003-05-20

申请号：US09983148

申请日：2001-10-23

申请人： Yoshiharu Kato ,  Satoru Kawamoto

发明人： Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C1124

CPC分类号： G11C7/227 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099

摘要： A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal &phgr;CPR. The signal &phgr;CPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.

公开(公告)号：US06297999B2

公开(公告)日：2001-10-02

申请号：US09784181

申请日：2001-02-16

申请人： Yoshiharu Kato ,  Satoru Kawamoto

发明人： Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C2900

CPC分类号： G11C29/50 ,  G11C11/401

摘要： The present invention provides a semiconductor memory device that performs a burn-in test. The device includes word lines, pairs of bit lines, memory cells, sense amplifiers connected to the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and a burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on the burn-in control signal The burn-in test control circuit includes a potential difference setting circuit for selecting one of the first word lines so to generate a potential difference between at least one of the pairs of bit lines. The sense amplifiers amplify the potential difference to provide the stress voltage between the word lines and the associated pair of bit lines and between the bit lines of that pair.

摘要翻译： 本发明提供一种执行老化测试的半导体存储器件。 该器件包括字线，位线对，存储器单元，连接到位线对的读出放大器，用于放大相关联的位线对之间的电位差，以及用于提供应力电压的老化测试控制电路 多个字线和位线对，以基于老化控制信号进行老化测试。老化测试控制电路包括：电位差设定电路，用于选择一个第一字线以产生 至少一对位线之间的电位差。 读出放大器放大电位差，以在字线和相关的位线对之间以及该对的位线之间提供应力电压。

公开(公告)号：US07580308B2

公开(公告)日：2009-08-25

申请号：US11812420

申请日：2007-06-19

申请人： Hajime Sato ,  Yuji Nakagawa ,  Satoru Kawamoto

发明人： Hajime Sato ,  Yuji Nakagawa ,  Satoru Kawamoto

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4068

摘要： A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.

摘要翻译： 用于半导体存储器件的刷新方法具有高抗噪性，较低的功耗和较低的成本。 在自刷新模式下未被选择的一个或多个存储单元块的所有字线被控制为具有基本上处于地平面的浮动电位。 即使当字线和位线短路时，该控制也可以防止可能由噪声引起的存储单元信息的破坏，并且还防止漏电流的产生。 不需要用于防止产生泄漏电流的保险丝等，从而实现较低的成本。