Electron beam lithography using an aperture having an array of repeated
unit patterns
    41.
    发明授权
    Electron beam lithography using an aperture having an array of repeated unit patterns 失效
    使用具有重复单元图案阵列的孔的电子束光刻

    公开(公告)号:US5250812A

    公开(公告)日:1993-10-05

    申请号:US858868

    申请日:1992-03-27

    IPC分类号: H01J37/317 H01J37/04

    摘要: An electron beam lithography apparatus is disclosed which has an aperture plate provided with an aperture including an array of repeated unit patterns and an ordinary aperture of a rectangular shape. A region free of the influence of a proximity effect is delineated using the former aperture, and a region affected by the proximity effect is delineated using the latter aperture. The number of repeated unit patterns included in the former aperture is determined considering the number of repeated unit patterns included in a pattern array to be delineated on a substrate. Thereby, the number of electron beam shots is reduced. A plurality of apertures having slightly different aperture widths may be provided for always keeping a pattern line width constant.

    摘要翻译: 公开了一种电子束光刻设备,其具有设置有包括重复单元图案阵列和矩形形状的普通孔径的孔的孔板。 使用前一个孔径来描绘没有接近效应的影响的区域,并且使用后一个孔来描绘受邻近效应影响的区域。 考虑包括在衬底上要描绘的图案阵列中的重复单位图案的数量来确定包括在前一孔径中的重复单位图案的数量。 因此,电子束拍摄的数量减少。 可以提供具有略微不同的孔径宽度的多个孔,以始终保持图案线宽度恒定。

    Defect inspection method and its system
    46.
    发明申请
    Defect inspection method and its system 有权
    缺陷检查方法及其系统

    公开(公告)号:US20090206252A1

    公开(公告)日:2009-08-20

    申请号:US12320574

    申请日:2009-01-29

    IPC分类号: G01N23/00

    摘要: A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.

    摘要翻译: 一种能够容易地管理半导体集成图案的致命缺陷的方法,该方法能够存储由半导体集成电路设计者设计的每个图案的设计数据,以及存储具有根据其设计意图排列的图案重要性级别的设计意图数据 分别。 该方法还可以预测由于目标曝光系统等的特性而系统地产生的缺陷,同时在预先进行的模拟中将每个设计的电路图案暴露并描绘到晶片上,并将这些缺陷存储为热点信息。 此外,该方法还能够将设计意图数据与热点信息组合,以限制可能包括关于对象半导体集成电路的特性的高可能性的系统缺陷的检查点,并显着缩短缺陷检查时间。