公开(公告)号：US10209573B2

公开(公告)日：2019-02-19

申请号：US14744392

申请日：2015-06-19

Applicant: Boe Technology Group Co., Ltd. ,  Beijing Boe Display Technology Co., Ltd.

Inventor： Xiaoxiang Zhang ,  Zheng Liu ,  Zongjie Guo ,  Zhichao Zhang ,  Mingxuan Liu ,  Xi Chen

IPC: G03F1/42 ,  G02F1/1339 ,  G03F1/54 ,  G02F1/1341 ,  G02F1/1333

Abstract: An UV curing mask plate, comprising: a mask layer, wherein: the mask layer is arranged on the substrate, and has a position corresponding to alignment marks, selection marks and an area not covered by the sealing frame glue to be cured; the material of the mask layer is a material with the function of blocking UV light.

公开(公告)号：US10084095B2

公开(公告)日：2018-09-25

申请号：US15322490

申请日：2016-03-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaolong Li ,  Zheng Liu ,  Xiaoyong Lu ,  Chunping Long ,  Huijuan Zhang

IPC: H01L31/0312 ,  H01L29/786 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L21/02

CPC classification number: H01L29/78609 ,  H01L21/02527 ,  H01L21/02598 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/043 ,  H01L29/045 ,  H01L29/1602 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/78621 ,  H01L29/78684 ,  H01L29/78696

Abstract: The embodiments of present disclosure provide a thin film transistor, a method for manufacturing the same, and an array substrate. The thin film transistor comprises an active layer provided on a substrate, the active layer including a middle channel region, a first high resistance region and a second high resistance region provided respectively on external sides of the middle channel region, a source region provided on an external side of the first high resistance region and a drain region provided on an external side of the second high resistance region, wherein a base material of the active layer is diamond single crystal. According to the thin film transistor, the method for manufacturing the same, and the array substrate provided in the embodiments of present disclosure, by providing high resistance regions on external sides of the middle channel region of the active layer, the carrier mobility is reduced and the leakage current of the thin film transistor made of single crystalline diamond is effectively suppressed.

公开(公告)号：US10008516B2

公开(公告)日：2018-06-26

申请号：US14428578

申请日：2014-07-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yueping Zuo ,  Zheng Liu

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L27/1262 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/78603 ,  H01L29/78675 ,  H01L29/78678

Abstract: The present disclosure relates to the field of TFT manufacturing process, and provides an LTPS TFT array substrate, its manufacturing method and a display device. The LTPS TFT array substrate includes contact holes through which a source electrode and a drain electrode of the array substrate are connected to an active layer, respectively, wherein a conductive pattern connected to the active layer is provided at a base portion of the contact hole. According to the present disclosure, it is able to form an excellent ohmic contact between the source/drain electrodes and the active layer after the contact holes have been etched, thereby to ensure the display quality of the display device.

公开(公告)号：US09899430B2

公开(公告)日：2018-02-20

申请号：US15089815

申请日：2016-04-04

Applicant: BOE Technology Group Co., Ltd. ,  Beijing BOE Display Technology Co., Ltd.

Inventor： Xiaoxiang Zhang ,  Tsung Chieh Kuo ,  Zheng Liu ,  Zhichao Zhang ,  Mingxuan Liu ,  Xi Chen

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/417

CPC classification number: H01L27/1255 ,  H01L27/124 ,  H01L27/1288 ,  H01L28/82 ,  H01L28/88 ,  H01L29/41733

Abstract: Embodiments of the present disclosure provide a GOA unit and a method for producing the same and a gate driver circuit, which are directed to a field of display technique. The GOA unit includes: a TFT module and a capacitor structure formed on a substrate. The TFT module includes a gate electrode, a source electrode and a drain electrode, and the capacitor structure includes a first electrode and a second electrode configured to form a first capacitor. The gate of the TFT module is located in a same layer as the first electrode of the capacitor structure, the source electrode and the drain electrode of the TFT module are located in a same layer as the second electrode of the capacitor structure, and the second electrode has a groove. Embodiments of the present application are used for a display apparatus.

公开(公告)号：US09793366B2

公开(公告)日：2017-10-17

申请号：US15131175

申请日：2016-04-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Dong Li ,  Xiaolong Li

IPC: H01L29/423 ,  H01L29/49 ,  H01L27/12 ,  H01L27/32 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/42372 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288 ,  H01L27/32 ,  H01L27/3225 ,  H01L27/3248 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66765 ,  H01L29/78678

Abstract: An array substrate, a method for fabricating the same, a display panel and a display device are disclosed. The array substrate comprises a display area and a non-display area that is outside the display area. The method comprises: forming a metal layer on a base substrate, the metal layer comprising a conductive pattern in the display area and a first electrode in the non-display area; forming a protective layer on the metal layer, a thickness of the protection layer in the non-display area being less than a thickness of the protection layer in the display area; forming a display electrode layer on the protection layer and removing the display electrode layer in the non-display area; and removing the protection layer in the non-display area.

公开(公告)号：US09761617B2

公开(公告)日：2017-09-12

申请号：US15106052

申请日：2016-01-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

Inventor： Zheng Liu ,  Tsung Chieh Kuo ,  Xi Chen ,  Xiaoxiang Zhang ,  Zhichao Zhang ,  Mingxuan Liu

IPC: H01L21/00 ,  H01L21/84 ,  G02F1/1343 ,  H01L27/12 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1333

CPC classification number: H01L27/1288 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2001/134372 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/77 ,  H01L27/12 ,  H01L29/66765

Abstract: A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a final via; and forming a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.

公开(公告)号：US20170194461A1

公开(公告)日：2017-07-06

申请号：US15350844

申请日：2016-11-14

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaolong Li ,  Zheng Liu ,  Dong Li ,  Huijuan Zhang ,  Jian Min

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786 ,  H01L21/3065

CPC classification number: H01L29/66757 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32132 ,  H01L29/78675

Abstract: A method for processing a polysilicon thin film and a method for fabricating a thin film transistor are provided. The method for processing a polysilicon thin film includes: etching the polysilicon thin film using etching particles. An angle between an incident direction of the etching particles and the polysilicon thin film is larger than 0° and less than 90°.

公开(公告)号：US20160372629A1

公开(公告)日：2016-12-22

申请号：US14436141

申请日：2014-07-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO.,LTD.

Inventor： Xiaoxiang Zhang ,  Zheng Liu ,  Zongjie Guo

IPC: H01L33/00 ,  H01L33/44 ,  H01L33/58 ,  H01L33/42

CPC classification number: H01L33/0095 ,  G02B5/003 ,  G02B27/2214 ,  H01L21/76807 ,  H01L21/7684 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3248 ,  H01L33/42 ,  H01L33/44 ,  H01L33/58 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0058

Abstract: The present invention provides a manufacturing method for a light barrier substrate which comprising steps of: forming a metal electrode pattern on a substrate through a first patterning process; forming an insulating layer above the substrate and the metal electrode pattern; forming a metal electrode via hole on the insulating layer and forming a channel pattern for a connecting line between a metal electrode and an exterior integrated circuit (IC) on the insulating layer, with a half tone make process, through a second patterning process; forming a transparent electrode layer pattern on the substrate on which the metal electrode via hole and the channel pattern are formed. The masking steps for forming the insulating layer and the transparent electrode layer may be decreased due to the half tone masking process, thus, the manufacturing process is simplified and the manufacturing efficiency is increased, and the cost for manufacturing the light barrier substrate is lowered because the mask is less used in the manufacturing process.

Abstract translation: 本发明提供一种光阻板基片的制造方法，包括以下步骤：通过第一图形化工艺在基片上形成金属电极图案; 在衬底上方形成绝缘层和金属电极图案; 在所述绝缘层上形成金属电极通孔，并通过第二图案化工艺，通过半色调制作工艺，在所述绝缘层上形成金属电极和外部集成电路（IC）之间的连接线的沟道图案; 在其上形成有金属电极通孔和沟道图案的基板上形成透明电极层图案。 用于形成绝缘层和透明电极层的掩模步骤可以由于半色调掩蔽处理而降低，因此，制造工艺简化并且制造效率提高，并且制造光阻垒基板的成本降低，因为 该掩模在制造过程中较少使用。

公开(公告)号：US09478562B2

公开(公告)日：2016-10-25

申请号：US14646416

申请日：2014-09-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Zheng Liu ,  Zuqiang Wang ,  Jang Soon Im

IPC: H01L21/00 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L27/32

CPC classification number: H01L27/1222 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/66757 ,  H01L29/78675 ,  H01L2227/323

Abstract: An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided. The manufacturing method of an array substrate includes forming an active material layer (501), a gate insulating layer (204) and a metal thin film (502) on a base substrate (201), and forming a pattern including an active layer (203) and a pattern including a gate electrode (205), a source electrode (206), a drain electrode (207), a gate line (1063) and a data line (1061) by a first patterning process; forming a passivation layer (301) on the base substrate (201), and forming a source contact hole (302), a drain contact hole (303), and an bridge-structure contact hole (1062a) by a second patterning process; forming a transparent conductive thin film (1401) on the base substrate (201), and removing the transparent conductive thin film (1404) partially, so that a source contact section (401), a drain contact section (402), a pixel electrode (403), and an bridge structure (1062) are formed. With the manufacturing method, the use number of patterning processes is decreased.

Abstract translation: 提供阵列基板及其制造方法，显示装置，薄膜​​晶体管及其制造方法。 阵列基板的制造方法包括在基底基板（201）上形成活性物质层（501），栅极绝缘层（204）和金属薄膜（502），形成包括活性层（203）的图案 ）和通过第一图案化工艺包括栅电极（205），源电极（206），漏电极（207），栅线（1063）和数据线（1061）的图案; 在所述基底基板上形成钝化层，通过第二构图工艺形成源极接触孔，漏极接触孔和桥接结构接触孔; 在所述基底基板上形成透明导电薄膜，将所述透明导电薄膜部分地去除，使得源极接触部分，漏极接触部分，像素电极， （403）和桥结构（1062）。 通过制造方法，图案化处理的使用次数减少。

公开(公告)号：US20150171224A1

公开(公告)日：2015-06-18

申请号：US14124104

申请日：2012-12-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Chunping Long ,  Jang Soon Im

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78606 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/6675

Abstract: Embodiments of the present invention relate to display technology field and provide a thin film transistor (1) and manufacturing method thereof, an array substrate, and a display device, and do not damage an active layer (12) of the thin film transistor while forming vias (16) over the source region (120) and the drain region (121) with via etching process. The thin film transistor (1) comprises a substrate (10), an active layer (12), a gate insulating layer (13), a gate (14) and an inter-layer insulating layer (17) disposed on the substrate (10), and further comprises: a conductive etching barrier layer (15) disposed on the active layer; the conductive etching barrier layer (15) being located to correspond to the source region (120) and the drain region (121) of the active layer (12) and vias (16) being formed over the source region (120) and the drain region (121) of the active layer (12) and not extending beyond edges of the conductive etching barrier layer (15).

Abstract translation: 本发明的实施例涉及显示技术领域并提供薄膜晶体管（1）及其制造方法，阵列基板和显示装置，并且不会在形成时损坏薄膜晶体管的有源层（12） 通过蚀刻工艺在源区（120）和漏区（121）之间的通路（16）。 薄膜晶体管（1）包括基板（10），有源层（12），栅极绝缘层（13），栅极（14）和布置在基板（10）上的层间绝缘层 ），还包括：设置在所述有源层上的导电蚀刻阻挡层（15） 所述导电蚀刻阻挡层（15）被定位成对应于有源层（12）的源极区域（120）和漏极区域（121）以及形成在源极区域（120）和漏极 （12）的区域（121），并且不延伸超过导电蚀刻阻挡层（15）的边缘。