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公开(公告)号：US08564115B2
公开(公告)日：2013-10-22
申请号：US13492220
申请日：2012-06-08
IPC分类号： H01L23/04
CPC分类号： H01L21/02 , B81B7/007 , B81B2207/07 , H01L23/52 , H01L29/84 , H01L2224/02166 , H01L2224/48091 , H01L2224/48465 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.
摘要翻译： 提出具有微机电（MEMS）元件的封装结构，其包括具有多个电连接焊盘和形成在其上的MEMS元件的芯片; 设置在所述芯片上用于覆盖所述MEMS元件的盖; 设置在每个电连接焊盘上的螺柱凸块; 形成在芯片上的密封剂，其中一部分柱状凸块从密封剂暴露出来; 以及金属导电层，形成在密封剂上并连接到凸块上。 本发明的特征在于直接完成晶片上的封装工艺，以便在更短的时间内制造更薄和更便宜的封装结构。 本发明还提供如上所述的用于制造封装结构的方法。
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公开(公告)号：US08420430B2
公开(公告)日：2013-04-16
申请号：US12769087
申请日：2010-04-28
申请人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
发明人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
CPC分类号： B81B7/0064 , B81B7/007 , B81B2207/095 , H01L21/56 , H01L23/315 , H01L23/552 , H01L24/48 , H01L2224/48227 , H01L2224/48465 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/1461 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.
摘要翻译： 提供具有至少MEMS元件的封装结构的制造方法，包括：制备具有电连接焊盘和所述至少MEMS元件的晶片; 设置用于覆盖所述至少一个MEMS元件的盖，所述盖具有在其上形成的金属层; 电连接焊盘和金属层与接合线; 形成用于覆盖盖子，接合线，电连接垫和金属层的密封剂; 去除所述密封剂的部分以将所述接合线分别分离成第一和第二子接合线，其中所述第一和第二次接合线的顶端被暴露，所述第一子接合线电连接到所述电连接焊盘，以及 所述第二子接合线电连接到所述金属层; 在所述密封剂上形成用于电连接到所述第一子接合线的金属迹线; 在金属痕迹上形成凸块; 并执行单独处理。
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公开(公告)号：US08183092B2
公开(公告)日：2012-05-22
申请号：US12829704
申请日：2010-07-02
申请人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L23/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01033 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.
摘要翻译： 提供了堆叠半导体结构及其制造方法。 该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面， 经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板， 接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。 本发明防止回流引起的污染，备有特殊的模具，并消除闪光。
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公开(公告)号：US20100267202A1
公开(公告)日：2010-10-21
申请号：US12829704
申请日：2010-07-02
申请人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L21/50
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L23/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01033 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.
摘要翻译： 提供了堆叠半导体结构及其制造方法。 该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面， 经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板， 接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。 本发明防止回流引起的污染，备有特殊的模具，并消除闪光。
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公开(公告)号：US07772685B2
公开(公告)日：2010-08-10
申请号：US11591974
申请日：2006-11-01
申请人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L23/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01033 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.
摘要翻译： 提供了堆叠半导体结构及其制造方法。 该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面， 经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板， 接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。 本发明防止回流引起的污染，备有特殊的模具，并消除闪光。
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公开(公告)号：US20090284851A1
公开(公告)日：2009-11-19
申请号：US12353750
申请日：2009-01-14
申请人： Chih-Ming Huang , Chih-Lun Chen
发明人： Chih-Ming Huang , Chih-Lun Chen
IPC分类号： G02B7/02
摘要： A device for locking lens and a method for the same are provided. The device is used in a voice-coil motor of a photographing module of a cell phone. The voice-coil motor has a lens-stand for a lens being turned to a locking depth inside. The device includes a circumgyration-stop instrument having a first sustaining surface, and a focusing ring having a turning end. A turn-locking length of the turning end is equal to the locking depth inside. The device includes a circumgyration-stop preventing a pressure being persisted to apply on the lens as the focusing ring finishes the turn of the lens. The first turn-stop surface props the first sustaining surface as the focusing ring is turned to an extremity of the turn-locking length. The focusing ring accordingly escapes the circumgyration-stop instrument for finishing the focusing of the lens in the lens-stand.
摘要翻译： 提供一种用于锁定镜头的装置及其方法。 该装置用于手机拍摄模块的音圈电机。 音圈电机具有用于透镜转向内部锁定深度的透镜架。 该装置包括具有第一维持表面的旋转停止装置和具有转向端的聚焦环。 转向端的转向锁定长度等于内部的锁定深度。 该装置包括环绕止动件，防止当聚焦环完成透镜转动时持续施加在透镜上的压力。 当聚焦环转到转向锁定长度的末端时，第一个转动表面支撑第一个维持表面。 聚焦环相应地逃避了旋转停止仪器，以完成镜头在镜头架中的聚焦。
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公开(公告)号：US20090261476A1
公开(公告)日：2009-10-22
申请号：US12148319
申请日：2008-04-18
IPC分类号： H01L23/482 , H01L21/60
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2221/68345 , H01L2224/24226 , H01L2224/82001 , H01L2225/1035 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311
摘要： A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface.
摘要翻译： 公开了一种半导体器件及其制造方法。 该方法包括以下步骤：提供具有布置在其上的导电电路的载体板和具有设置在其上的焊料焊盘的有源表面的多个芯片，其中导电凸块设置在焊盘上; 将芯片安装在载板上; 用电介质层填充芯片之间的间隔，并在每个芯片周边的电介质层中形成开口以露出导电电路; 在所述电介质层的开口部和所述芯片的有源面的外围形成金属层，用于电连接所述导电凸块和所述导电电路; 并沿着芯片之间的电介质层切割并去除载体板以分离每个芯片并使导电电路与非活性表面相接触。
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公开(公告)号：US07508066B2
公开(公告)日：2009-03-24
申请号：US11267632
申请日：2005-11-03
申请人： Chien-Ping Huang , Chih-Ming Huang
发明人： Chien-Ping Huang , Chih-Ming Huang
CPC分类号： H01L23/3677 , H01L21/4871 , H01L21/561 , H01L23/3107 , H01L23/3128 , H01L23/367 , H01L23/3733 , H01L23/4334 , H01L23/49548 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/16245 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/351 , Y10T29/49126 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink.
摘要翻译： 提供散热半导体封装及其制造方法。 半导体芯片安装在芯片载体上。 散热器安装在芯片上，并且包括绝缘芯层，形成在绝缘芯层的上表面和下表面中的每一个上的薄金属层和形成在绝缘芯层中的热通孔。 进行成型工艺以用密封剂封装芯片和散热器以形成封装单元。 执行单个处理以周边地切割包装单元。 在散热器的上表面上的薄金属层上方的一部分密封剂被去除，使得散热器的上表面上的薄金属层被暴露，并且由芯片产生的热可以通过热量消散 水槽。
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公开(公告)号：US20090039527A1
公开(公告)日：2009-02-12
申请号：US12221725
申请日：2008-08-06
CPC分类号： H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L2224/05001 , H01L2224/056 , H01L2224/13 , H01L2224/13025 , H01L2224/16146 , H01L2224/94 , H01L2224/97 , H01L2924/19104 , H01L2924/19105 , H01L2924/00014 , H01L2224/81 , H01L2224/83
摘要： A sensor-type package and a method for fabricating the same are provided. A wafer having a plurality of semiconductor chips is provided, wherein a plurality of holes are formed on a first surface of each of the semiconductor chips, and a plurality of metallic pillars formed in the holes and a plurality of bond pads connected to the metallic pillars form through silicon vias (TSVs). A groove is formed on a second surface of each of the semiconductor chips to expose the metallic pillars. A plurality of sensor chips having TSVs are stacked in the grooves of the semiconductor chips and electrically connected to the exposed metallic pillars. A transparent cover is mounted onto the second surfaces of the semiconductor chips to cover the grooves. A plurality of conductive components are implanted on the bond pads of the semiconductor chips. The wafer is cut along borders among the semiconductor chips.
摘要翻译： 提供了一种传感器型封装及其制造方法。 提供具有多个半导体芯片的晶片，其中在每个半导体芯片的第一表面上形成多个孔，并且形成在孔中的多个金属柱和连接到金属柱的多个接合焊盘 通过硅通孔（TSV）形成。 在每个半导体芯片的第二表面上形成凹槽以暴露金属柱。 具有TSV的多个传感器芯片堆叠在半导体芯片的凹槽中并电连接到暴露的金属柱。 透明盖安装在半导体芯片的第二表面上以覆盖凹槽。 在半导体芯片的接合焊盘上注入多个导电元件。 在半导体芯片之间沿着边缘切割晶片。
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公开(公告)号：US20090014860A1
公开(公告)日：2009-01-15
申请号：US12011832
申请日：2008-01-29
CPC分类号： H01L25/0652 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73215 , H01L2224/73265 , H01L2224/92247 , H01L2225/06562 , H01L2924/00012
摘要： A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products.
摘要翻译： 提供了一种多芯片堆叠结构及其制造方法。 该制造方法包括以下步骤：提供具有与其相对的第一表面和第二表面的芯片载体和至少安装在第一表面上的第一芯片和第二芯片; 通过多个接合线将芯片电连接到芯片载体上; 并且通过其间放置的膜将第一和第二芯片上的至少第三芯片堆叠起来，其中第三芯片逐步堆叠在第一芯片上，并且连接到第二芯片的键合线的至少一部分被膜覆盖， 并通过接合线电连接第三芯片和芯片载体，从而能够将多个芯片堆叠在芯片载体上，以增强电子产品的电气性能。
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