公开(公告)号：US20140027871A1

公开(公告)日：2014-01-30

申请号：US13561671

申请日：2012-07-30

申请人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

发明人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

IPC分类号： H01L27/14

CPC分类号： G01T1/247 ,  G01N27/403 ,  G01T3/08 ,  H01L27/14 ,  H01L27/14681 ,  H01L31/022408 ,  H01L31/035272 ,  H01L31/1105 ,  H01L31/115 ,  H01L31/118

摘要： A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

摘要翻译： 传感器包括集电极，发射极和形成为反相双极结型晶体管的基极区势垒，其具有形成基极的基极以激活反相双极结型晶体管。 由集电极，发射极和基极区域与基底基板相对的方式形成电平表面，使得当电平表面暴露于电荷时，在双极结晶体管的操作期间测量电荷。

公开(公告)号：US20120298531A1

公开(公告)日：2012-11-29

申请号：US13571389

申请日：2012-08-10

申请人： Donald Dorman ,  Tak Ning ,  Sufi Zafar

发明人： Donald Dorman ,  Tak Ning ,  Sufi Zafar

IPC分类号： G01N27/414

CPC分类号： G01N27/4145 ,  G01N27/3271 ,  G01N27/3335 ,  G01N27/414

摘要： A method for operating a sensor for biomolecules or charged ions, the sensor comprising a first field effect transistor (FET) and a second FET, wherein the first FET and the second FET comprise a shared node includes placing an electrolyte containing the biomolecules or charged ions on a sensing surface of the sensor, the electrolyte comprising a gate of the second FET; applying an inversion voltage to a gate of the first FET; making a first electrical connection to an unshared node of the first FET; making a second electrical connection to unshared node of the second FET; determining a change in a drain current flowing between the unshared node of the first FET and the unshared node of the second FET; and determining an amount of biomolecules or charged ions contained in the electrolyte based on the determined change in the drain current.

摘要翻译： 一种用于操作用于生物分子或带电离子的传感器的方法，所述传感器包括第一场效应晶体管（FET）和第二FET，其中所述第一FET和所述第二FET包括共享节点，包括放置含有所述生物分子或带电离子的电解质 在所述传感器的感测表面上，所述电解质包括所述第二FET的栅极; 对第一FET的栅极施加反转电压; 与第一FET的非共享节点进行第一电连接; 与第二FET的非共享节点进行第二电连接; 确定在所述第一FET的非共享节点和所述第二FET的非共享节点之间流动的漏极电流的变化; 以及基于确定的漏极电流的变化来确定电解质中包含的生物分子或带电离子的量。

公开(公告)号：US08304836B2

公开(公告)日：2012-11-06

申请号：US12620234

申请日：2009-11-17

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/70

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US08288237B2

公开(公告)日：2012-10-16

申请号：US12541575

申请日：2009-08-14

申请人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Dianne L. Lacey ,  Fenton R. Feeney ,  Katherine L. Saenger ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Dianne L. Lacey ,  Fenton R. Feeney ,  Katherine L. Saenger ,  Sufi Zafar

IPC分类号： H01L21/336

CPC分类号： H01L29/4966 ,  C23C14/0036 ,  C23C14/0635 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device.

摘要翻译： 提供了包含TiC的复合金属，其是在包括高k电介质和界面层的栅极堆叠上具有约4.75至约5.3，优选约5e的功函数的功函数的热电稳定的p型金属，以及 制造TiC复合金属的方法。 此外，本发明的TiC金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许在p金属氧化物半导体（pMOS）器件中非常有侵蚀性的等效氧化物厚度（EOT）和反型层厚度缩小至低于Å 。

公开(公告)号：US20110115027A1

公开(公告)日：2011-05-19

申请号：US12620234

申请日：2009-11-17

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/263

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US20080299730A1

公开(公告)日：2008-12-04

申请号：US12190129

申请日：2008-08-12

申请人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L21/336 ,  C23C14/34

CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

摘要翻译： 包含MoxNy的复合金属是具有在包括高k电介质和界面层的栅叠层上热稳定的功函数为约4.75至约5.3，优选约5e的功函数的p型金属，以及 制造MOxNy复合金属的方法。 此外，本发明的MOxNy金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许在p金属氧化物半导体（pMOS）器件中非常有侵蚀性的等效氧化物厚度（EOT）和低于14的反型层厚度标度 。 在上式中，M是选自元素周期表第IVB，VB，VIB或VIIB族的金属，x为约5至约40原子％，y为约5至约40原子％。

公开(公告)号：US07436034B2

公开(公告)日：2008-10-14

申请号：US11311455

申请日：2005-12-19

申请人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L21/00

CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (PMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

摘要翻译： 一种复合金属，其包含具有约4.75至约5.3，优选约5eV的功函数的p型金属，其在一个或多个金属上是热稳定的 提供了包括高k电介质和界面层的栅极叠层以及制造复合金属的方法。 此外，本发明的金属氧化物金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许非常有效的等效氧化物厚度（EOT）和反演 在p-金属氧化物半导体（PMOS）器件中的层厚度缩小到14埃以下。 在上式中，M是选自元素周期表第IVB，VB，VIB或VIIB族的金属，x为约5至约40原子％，y为约5至约40原子％。

公开(公告)号：US07115959B2

公开(公告)日：2006-10-03

申请号：US10873733

申请日：2004-06-22

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evengi Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph P. Shepard, Jr. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evengi Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph P. Shepard, Jr. ,  Sufi Zafar

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

公开(公告)号：US06413819B1

公开(公告)日：2002-07-02

申请号：US09595821

申请日：2000-06-16

申请人： Sufi Zafar ,  Ramachandran Muralidhar ,  Bich-Yen Nguyen ,  Sucharita Madhukar ,  Daniel T. Pham ,  Michael A. Sadd ,  Chitra K. Subramanian

发明人： Sufi Zafar ,  Ramachandran Muralidhar ,  Bich-Yen Nguyen ,  Sucharita Madhukar ,  Daniel T. Pham ,  Michael A. Sadd ,  Chitra K. Subramanian

IPC分类号： H01L21336

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/7883 ,  H01L29/7888

摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).

摘要翻译： 提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。 该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。 然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。 该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。 一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。 在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。 然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。 然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

公开(公告)号：US5750419A

公开(公告)日：1998-05-12

申请号：US803789

申请日：1997-02-24

申请人： Sufi Zafar

发明人： Sufi Zafar

IPC分类号： H01L21/8247 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01G7/06 ,  H01L21/8239

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： One or more dielectric layers (32, 52) are formed over a ferroelectric capacitor (24) of a FENVM cell, where that the tension within the dielectric layers (32, 52) overlying the ferroelectric capacitor (24) is kept relatively low. By keeping the tension relatively low, the nonvolatile polarization of the FENVM cell is maintained during back end processing steps of a fabrication process.

摘要翻译： 在FENVM单元的铁电电容器（24）上形成一个或多个电介质层（32,52），其中覆盖铁电电容器（24）的电介质层（32,52）内的张力保持相对较低。 通过保持张力相对较低，在制造过程的后端处理步骤期间保持FENVM单元的非极性极化。