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70 条记录 (耗时 0.033 秒)

    Field effect transistor
    41.
    发明授权
    Field effect transistor 有权
    场效应晶体管

    公开(公告)号：US07767518B2

    公开(公告)日：2010-08-03

    申请号：US12266876

    申请日：2008-11-07

    申请人： Helmut Tews

    发明人： Helmut Tews

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10841 ,  H01L27/1082 ,  H01L27/10823 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/161 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827 ,  Y10T29/41

    摘要： A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor dielectric. In addition, the control region may comprise a monocrystalline material.

    摘要翻译： 提供场效应晶体管。 场效应晶体管包括沟道区，导电沟道连接区和控制区。 导电沟道连接区域与晶体管电介质连接在沟道区域上。 控制区域通过晶体管电介质与沟道区域分离。 此外，控制区域可以包括单晶材料。

    Hard mask arrangement
    45.
    发明申请
    Hard mask arrangement 审中-公开
    硬面罩布置

    公开(公告)号：US20060234138A1

    公开(公告)日：2006-10-19

    申请号：US11393017

    申请日：2006-03-30

    申请人： Rodger Fehlhaber ,  Helmut Tews

    发明人： Rodger Fehlhaber ,  Helmut Tews

    IPC分类号： G03F1/00 ,  H01L21/311

    CPC分类号： H01L21/0337 ,  H01L21/0338

    摘要： An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased.

    摘要翻译： 描述了具有第一和第二互连的互连连接结构以及将第一互连电连接到第二互连的多个连接元件。 多个连接元件相对于互连件的覆盖取向横向地形成在第一和第二互连件的横向区域中。 中心区域可以没有连接元件，使得连接结构的电迁移特性得到改善并且载流能力增加。

    Gate processing method with reduced gate oxide corner and edge thinning
    47.
    发明授权
    Gate processing method with reduced gate oxide corner and edge thinning 有权
    栅极处理方法具有减少的栅氧化物角和边缘变薄

    公开(公告)号：US06656798B2

    公开(公告)日：2003-12-02

    申请号：US09965919

    申请日：2001-09-28

    申请人： Helmut Tews ,  Oleg Gluschenkov ,  Mary Weybright

    发明人： Helmut Tews ,  Oleg Gluschenkov ,  Mary Weybright

    IPC分类号： H01L21336

    CPC分类号： H01L29/517 ,  H01L21/28238 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/42368

    摘要： Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.

    摘要翻译： 公开了一种在半导体晶片上处理半导体栅极结构的方法，该方法包括提供半导体结构，该半导体结构具有覆盖有由一个或多个隔离沟槽限定的焊盘氧化物层的有源器件区域，通过增厚所述焊盘来提供牺牲氧化物层 使用所述增厚衬垫氧化物层作为用于器件注入的牺牲氧化物层，在使用之后剥离所述牺牲衬垫氧化物层，并用最终栅极氧化物层封装所述半导体栅极。

    Method of forming low-leakage on-chip capacitor
    48.
    发明授权
    Method of forming low-leakage on-chip capacitor 失效
    形成低漏电片上电容器的方法

    公开(公告)号：US06451662B1

    公开(公告)日：2002-09-17

    申请号：US09970635

    申请日：2001-10-04

    申请人： Michael Chudzik ,  Oleg Gluschenkov ,  Raj Jammy ,  Uwe Schroeder ,  Helmut Tews

    发明人： Michael Chudzik ,  Oleg Gluschenkov ,  Raj Jammy ,  Uwe Schroeder ,  Helmut Tews

    IPC分类号： H01L2120

    CPC分类号： H01L27/10861 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31662 ,  H01L21/32105

    摘要： An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

    摘要翻译： 通过在形成节点介质层期间通过执行自由基增强快速热氧化（FRE RTO）步骤而改进的介电常数形成改进的节点电介质层的工艺形成改进的电容器。 使用FRE RTO步骤代替常规炉氧化步骤产生具有更高介电常数和较高电容的清洁氧化物。 本发明的其它具体实施方案包括通过远程等离子体氮化（RPN），快速热氮化（RTN），去耦等离子体氮化（DPN）或其它氮化方法进行的一个或多个另外的氮化步骤改进的节点电介质层; 选择性氧化; 使用金属层而不是SiN层作为电介质基底; 和金属层的选择性氧化。

    Structure and method for improved isolation in trench storage cells
    49.
    发明授权
    Structure and method for improved isolation in trench storage cells 失效
    用于改善沟槽存储单元隔离的结构和方法

    公开(公告)号：US06437401B1

    公开(公告)日：2002-08-20

    申请号：US09824957

    申请日：2001-04-03

    申请人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

    发明人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

    IPC分类号： H01L2976

    CPC分类号： H01L27/1087 ,  H01L27/10861 ,  H01L27/10864 ,  H01L29/945

    摘要： A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

    摘要翻译： 提供了用于改善电荷保留的沟槽电容器结构及其制造方法。 在p型导电性半导体衬底中形成沟槽。 隔离套环位于沟槽的上部。 与沟槽上部相邻的衬底包含第一n +型导电区​​和第二n +型导电区​​。 这些区域各自邻接沟槽的壁并且被p型导电性半导体衬底的一部分垂直分开。 围绕沟槽的周边的空隙形成沟槽的壁，并且位于第一和第二n +型导电区​​域之间的衬底中。