公开(公告)号：US10707303B1

公开(公告)日：2020-07-07

申请号：US16264273

申请日：2019-01-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Hui Zang ,  Zhenyu Owen Hu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

Abstract: A semiconductor device, comprising a semiconductor substrate; an isolation layer disposed on the semiconductor substrate; a first active region and a second active region disposed at least partially above the isolation layer; a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region; and an isolation pillar disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation pillar has an inverted-T shape. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device.

公开(公告)号：US10692987B2

公开(公告)日：2020-06-23

申请号：US16164867

申请日：2018-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Guowei Xu ,  Hui Zang

IPC: H01L29/66 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/78

Abstract: The disclosure provides an integrated circuit (IC) structure including a first spacer on a semiconductor fin adjacent a first portion of the gate structure, and having a first height above the semiconductor fin; a second spacer on the semiconductor fin adjacent the first spacer, such that the first spacer is horizontally between the first portion of the gate structure and a lower portion of the outer; and a gate cap positioned over the first portion of the gate structure and on the second spacer above the semiconductor fin. The gate cap defines an air gap horizontally between the first portion of the gate structure and an upper portion of the second spacer, and vertically between an upper surface of the first spacer and a lower surface of the gate cap.

公开(公告)号：US10685881B2

公开(公告)日：2020-06-16

申请号：US16112511

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Haiting Wang

IPC: H01L21/70 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532 ,  H01L29/66

Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced risk of short circuits between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including a fin structure comprising a fin body, source/drain regions, and a metal formation disposed above the source/drain regions, wherein the metal formation has a first height; and a gate structure between the source/drain regions, wherein each gate structure comprises spacers in contact with the metal formation, wherein the spacers have a second height less than the first height, a metal plug between the spacers and below the second height, and a T-shaped cap above the metal plug and having the first height.

公开(公告)号：US20200135723A1

公开(公告)日：2020-04-30

申请号：US16170117

申请日：2018-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Chung Foong Tan ,  Guowei Xu ,  Ruilong Xie ,  Scott H. Beasor ,  Liu Jiang

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234

Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

公开(公告)号：US20200127109A1

公开(公告)日：2020-04-23

申请号：US16164867

申请日：2018-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Guowei Xu ,  Hui Zang

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535

Abstract: The disclosure provides an integrated circuit (IC) structure including a first spacer on a semiconductor fin adjacent a first portion of the gate structure, and having a first height above the semiconductor fin; a second spacer on the semiconductor fin adjacent the first spacer, such that the first spacer is horizontally between the first portion of the gate structure and a lower portion of the outer; and a gate cap positioned over the first portion of the gate structure and on the second spacer above the semiconductor fin. The gate cap defines an air gap horizontally between the first portion of the gate structure and an upper portion of the second spacer, and vertically between an upper surface of the first spacer and a lower surface of the gate cap.

公开(公告)号：US10600914B2

公开(公告)日：2020-03-24

申请号：US15869541

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Zhao ,  Ming Hao Tang ,  Haiting Wang ,  Rui Chen ,  Yuping Ren ,  Hui Zang ,  Scott H. Beasor ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/11 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.

公开(公告)号：US20190393077A1

公开(公告)日：2019-12-26

申请号：US16016910

申请日：2018-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chih-Chiang Chang ,  Haifeng` Sheng ,  Jiehui Shu ,  Haigou Huang ,  Pei Liu ,  Jinping Liu ,  Haiting Wang ,  Daniel J. Jaeger

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

公开(公告)号：US20190341475A1

公开(公告)日：2019-11-07

申请号：US15970217

申请日：2018-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US20190312117A1

公开(公告)日：2019-10-10

申请号：US15949730

申请日：2018-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Hong Yu ,  Yanping Shen ,  Wei Hong ,  Xing Zhang ,  Ruilong Xie ,  Haiting Wang ,  Hui Zhan ,  Yong Jun Shi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/45 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.

公开(公告)号：US20190295898A1

公开(公告)日：2019-09-26

申请号：US16403745

申请日：2019-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Daniel Jaeger ,  Chanro Park ,  Laertis Economikos ,  Haiting Wang ,  Hui Zang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L21/311

Abstract: Structures and methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. A sacrificial layer may be disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. Alternatively, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.